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Migrate quilt patches into source - #192

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RadxaStephen merged 38 commits into
radxa:u-boot-dlan17from
vamrs-feng:u-boot-dlan17
Aug 16, 2026
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Migrate quilt patches into source#192
RadxaStephen merged 38 commits into
radxa:u-boot-dlan17from
vamrs-feng:u-boot-dlan17

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CodeChenL and others added 30 commits August 12, 2026 15:34
Directly copied from radxa-cubie-a7a,
only modified some name field

Signed-off-by: Jiali Chen <chenjiali@radxa.com>
Ensure stable operation of 1GB DDR
Add pin control configuration for I2C0 on PG8 (SDA) and PG9 (SCL) in the
sun60i-a733 SoC. This enables I2C0 usage on platforms utilizing these pins.

Signed-off-by: Feng Zhang <feng@radxa.com>
Enable CONFIG_FDT_FIXUP_PARTITIONS in radxa-cubie-a7s_defconfig to allow
runtime partition table fixup in the device tree (e.g., for U-Boot or
kernel-based flash layout adjustments).
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Implement sunxi (Allwinner) GPADC driver, referenced and
modified from the U-Boot 2018 implementation in Allwinner TinaSDK.

Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Lower FIT load address to 0x47a00000 and increase malloc_simple heap
to 0x110000 for SPL DRAM stack phase.

Signed-off-by: Feng Zhang <feng@radxa.com>
Set initrd_high=0xffffffff to enable zero-copy ramdisk mode. This prevents
U-Boot from relocating ramdisk and uses the original address directly,
avoiding conflicts with:
- Display framebuffer at 0x46400000
- BL31 reserved region at 0x48000000
- U-Boot runtime memory

When initrd_high is set to specific addresses like 0x46400000 or
0x4FF00000, ramdisk relocation may cause kernel boot hangs or
FDT corruption (FDT_ERR_BADMAGIC).

Zero-copy mode ensures ramdisk stays at its loaded location without
additional memory allocation, providing more reliable boot behavior.

Signed-off-by: Feng Zhang <feng@radxa.com>
Add sunxi_get_serial() to derive serial number from chipid
in the same format as Linux /sys/class/sunxi_info/sys_info.

Add 'sid' U-Boot command to display chipid and serial.

Signed-off-by: Feng Zhang <feng@radxa.com>
Try EEPROM first for MAC address, fallback to deriving it from
chipid (SID efuse) if EEPROM is unavailable or returns invalid MAC.

Signed-off-by: Feng Zhang <feng@radxa.com>
U-Boot initializing USB controllers (EHCI/OHCI/DWC3) left the EHCI
controller in a non-halted state, causing Linux's ehci-sunxi driver
to fail usb_add_hcd() during probe.

Changes:
- ehci-hcd.c: force HCRESET in ehci_shutdown() when graceful stop fails
- ehci-generic.c, ohci-generic.c, xhci-dwc3.c: add DM_FLAG_OS_PREPARE
  so dm_remove_devices_active() auto-cleans USB before booting kernel

Signed-off-by: Feng Zhang <feng@radxa.com>
The R_PIO controller on A733 (and potentially other SoCs) has a different
register bank spacing (0x30 bytes) compared to the main PIO controller
(0x80 bytes). Previously all pinctrl operations hardcoded
SUNXI_PINCTRL_BANK_SIZE (0x80), causing register accesses to R_PIO banks
beyond the first one to hit wrong offsets.

Add a sunxi_pinctrl_bank_size() helper that detects R_PIO controllers by
checking desc->first_bank == SUNXI_GPIO_L, and returns the appropriate
bank size (SUNXI_R_PINCTRL_BANK_SIZE for R_PIO, SUNXI_PINCTRL_BANK_SIZE
otherwise). Apply this to all register offset calculations in pinmux,
pinconf, and gpio bank binding paths.

For non-A733 platforms, SUNXI_R_PINCTRL_BANK_SIZE equals
SUNXI_PINCTRL_BANK_SIZE, so this change has no effect on them.

Signed-off-by: Feng Zhang <feng@radxa.com>
Add a fixed regulator "usb-host-en" controlled by PM5 (R_PIO port M pin 5)
to enable USB host port power. The regulator is set to always-on and
boot-on so USB host ports are powered up early in the boot process.

Signed-off-by: Feng Zhang <feng@radxa.com>
Read fdt_addr_r from U-Boot environment and pass it to ATF via
SMC call (ARM_SVC_ARISC_STARTUP). Validate the device tree magic
(0xedfe0dd0) before sending and print warning if fdt_addr_r is
not set, so power management on ARISC can access the full device
tree for PMIC and regulator configuration.

Signed-off-by: Feng Zhang <feng@radxa.com>
In the extlinux/sysboot boot flow, call sunxi_boot_arisc after
the device tree has been loaded to fdt_addr_r but before bootm/
booti starts the kernel. This ensures the ARISC coprocessor
receives a valid device tree for power management, replacing
the previous preboot-based approach that ran before extlinux
had populated fdt_addr_r.

Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
vamrs-feng and others added 8 commits August 12, 2026 15:34
The A733 BootROM reports SPI NOR boot source as 0x43 when loading
the SPL from the 256 KiB fallback location. Map this value to the
SPL SPI boot device and account for the fallback offset when locating
the FIT image.

Add A733 support to the sunxi SPL SPI loader, including the SPI0
controller base, pinmux, module clock, bus gate and reset setup.

This allows SPL to initialize DRAM and load the FIT containing BL31,
SCP and U-Boot proper directly from SPI NOR.

Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
The A733 BootROM reports UFS boot with boot source value 0x15.
Map this value to BOOT_DEVICE_UFS so SPL selects the UFS loader.

Propagate errors from SCSI scanning and UFS command submission instead
of continuing after initialization or transfer failures. For SPL UFS
boot, limit the LUN scan range based on the configured raw U-Boot
device number.

These changes provide the code support required for UFS boot in the
A733 SPL.

Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
The size-optimized SPL device tree drops the clock and pinctrl data
needed by the driver-model MMC path. Set up the A733 MMC clock gate,
reset and pins directly in SPL.

Add the required controller settling intervals and wait for FIFO reset
completion so SD boot remains reliable when UFS support enables driver
model in SPL.

Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>
Signed-off-by: Feng Zhang <feng@radxa.com>

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LGTM

@RadxaStephen
RadxaStephen merged commit ea51f83 into radxa:u-boot-dlan17 Aug 16, 2026
@vamrs-feng
vamrs-feng deleted the u-boot-dlan17 branch August 17, 2026 02:32
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4 participants