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8379867: C2 VectorAPI: Rename TypeVectMask -> TypePVectMask for clarity #30812

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8379867: C2 VectorAPI: Rename TypeVectMask -> TypePVectMask for clarity #30812

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4b47e93
8379867: C2 VectorAPI: Rename TypeVectMask -> TypePVectMask for clarity
dev-jonghoonpark Apr 19, 2026
ce05b3c
Merge remote-tracking branch 'origin/master' into JDK-8379867
dev-jonghoonpark Apr 23, 2026
ef86f74
trigger ci
dev-jonghoonpark Apr 30, 2026
c237fe5
Merge remote-tracking branch 'origin/master' into JDK-8379867
dev-jonghoonpark Apr 30, 2026
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6 changes: 3 additions & 3 deletions src/hotspot/cpu/aarch64/aarch64.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -1986,7 +1986,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r

assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");

if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
if (src_hi != OptoReg::Bad && !bottom_type()->isa_pvectmask()) {
assert((src_lo&1)==0 && src_lo+1==src_hi &&
(dst_lo&1)==0 && dst_lo+1==dst_hi,
"expected aligned-adjacent pairs");
Expand All @@ -2001,7 +2001,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
int src_offset = ra_->reg2offset(src_lo);
int dst_offset = ra_->reg2offset(dst_lo);

if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
uint ireg = ideal_reg();
DEBUG_ONLY(int algm = MIN2(RegMask::num_registers(ireg), (int)Matcher::stack_alignment_in_slots()) * VMRegImpl::stack_slot_size);
assert((src_lo_rc != rc_stack) || is_aligned(src_offset, algm), "unaligned vector spill sp offset %d (src)", src_offset);
Expand Down Expand Up @@ -2149,7 +2149,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
} else {
st->print("%s", Matcher::regName[dst_lo]);
}
if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
int vsize = 0;
switch (ideal_reg()) {
case Op_VecD:
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/aarch64/aarch64_vector.ad
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Expand Up @@ -452,11 +452,11 @@ source %{
// On architectures that do not support predicate, masks are stored in
// general vector registers (TypeVect) with sizes ranging from TypeVectA
// to TypeVectX based on the vector size in bytes.
assert(vt->isa_vectmask() == nullptr, "mask type is not matched");
assert(vt->isa_pvectmask() == nullptr, "mask type is not matched");
return false;
}

assert(vt->isa_vectmask() != nullptr, "expected TypeVectMask on SVE");
assert(vt->isa_pvectmask() != nullptr, "expected TypePVectMask on SVE");
switch (opcode) {
case Op_VectorMaskToLong:
case Op_VectorLongToMask:
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/aarch64/aarch64_vector_ad.m4
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Expand Up @@ -442,11 +442,11 @@ source %{
// On architectures that do not support predicate, masks are stored in
// general vector registers (TypeVect) with sizes ranging from TypeVectA
// to TypeVectX based on the vector size in bytes.
assert(vt->isa_vectmask() == nullptr, "mask type is not matched");
assert(vt->isa_pvectmask() == nullptr, "mask type is not matched");
return false;
}

assert(vt->isa_vectmask() != nullptr, "expected TypeVectMask on SVE");
assert(vt->isa_pvectmask() != nullptr, "expected TypePVectMask on SVE");
switch (opcode) {
case Op_VectorMaskToLong:
case Op_VectorLongToMask:
Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/riscv/riscv.ad
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Expand Up @@ -1580,7 +1580,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r

assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");

if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
if (src_hi != OptoReg::Bad && !bottom_type()->isa_pvectmask()) {
assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
(dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
"expected aligned-adjacent pairs");
Expand Down Expand Up @@ -1616,7 +1616,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
} else {
ShouldNotReachHere();
}
} else if (bottom_type()->isa_vectmask() && masm) {
} else if (bottom_type()->isa_pvectmask() && masm) {
int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
// stack to stack
Expand Down Expand Up @@ -1718,7 +1718,7 @@ uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *r
} else {
st->print("%s", Matcher::regName[dst_lo]);
}
if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
if (bottom_type()->isa_vect() && !bottom_type()->isa_pvectmask()) {
int vsize = 0;
if (ideal_reg() == Op_VecA) {
vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/riscv/riscv_v.ad
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Expand Up @@ -181,8 +181,8 @@ source %{
}

bool Matcher::mask_op_prefers_predicate(int opcode, const TypeVect* vt) {
// Prefer predicate if the mask type is "TypeVectMask".
return vt->isa_vectmask() != nullptr;
// Prefer predicate if the mask type is "TypePVectMask".
return vt->isa_pvectmask() != nullptr;
}
%}

Expand Down
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