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csr_regfile: Fix SBE/UBE when S/U-mode disabled #3302

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csr_regfile: Fix SBE/UBE when S/U-mode disabled #3302

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8 changes: 4 additions & 4 deletions core/csr_regfile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1559,17 +1559,17 @@ module csr_regfile
mstatus_d.wpri2 = 1'b0;
mstatus_d.wpri0 = 1'b0;
// Mirror MBE
mstatus_d.sbe = mstatus_d.mbe;
mstatus_d.ube = mstatus_d.mbe;
mstatus_d.sbe = CVA6Cfg.RVS ? mstatus_d.mbe : 1'b0;
mstatus_d.ube = CVA6Cfg.RVU ? mstatus_d.mbe : 1'b0;
// this register has side-effects on other registers, flush the pipeline
flush_o = 1'b1;
end
riscv::CSR_MSTATUSH: begin
if (CVA6Cfg.XLEN == 32) begin
mstatus_d.mbe = ((csr_wdata & riscv::MSTATUSH_MBE) != 0);
// Mirror MBE
mstatus_d.sbe = mstatus_d.mbe;
mstatus_d.ube = mstatus_d.mbe;
mstatus_d.sbe = CVA6Cfg.RVS ? mstatus_d.mbe : 1'b0;
mstatus_d.ube = CVA6Cfg.RVU ? mstatus_d.mbe : 1'b0;
// this register has side-effects on other registers, flush the pipeline
flush_o = 1'b1;
end else begin
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