Skip to content

Fix aes32esi bug #3243

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
antonangeloff wants to merge 3 commits into
base: master
Choose a base branch
from
+2 −2
Open

Fix aes32esi bug #3243

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
f04063e
Assign orig_instr_o if ZKN is enabled
antonangeloff Mar 22, 2026
9334ce6
Auto-enabled RVB if ZKN is set
antonangeloff Mar 22, 2026
f23ad6b
Use boolean operator
antonangeloff Mar 23, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion core/decoder.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1846,7 +1846,7 @@ module decoder
if (~ex_i.valid) begin
// if we didn't already get an exception save the instruction here as we may need it
// in the commit stage if we got a access exception to one of the CSR registers
if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF)
if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF || CVA6Cfg.ZKN)
orig_instr_o = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i};
if (CVA6Cfg.TvalEn)
instruction_o.ex.tval = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i};
Expand Down
2 changes: 1 addition & 1 deletion core/include/build_config_pkg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ package build_config_pkg;
cfg.XF16ALT = CVA6Cfg.XF16ALT;
cfg.XF8 = CVA6Cfg.XF8;
cfg.RVA = CVA6Cfg.RVA;
cfg.RVB = CVA6Cfg.RVB;
cfg.RVB = CVA6Cfg.RVB || CVA6Cfg.ZKN; // ZKN requires RVB
cfg.ZKN = CVA6Cfg.ZKN;
cfg.RVV = CVA6Cfg.RVV;
cfg.RVC = CVA6Cfg.RVC;
Expand Down
Loading