Argus core vibe coded by Fulvio

cores/argus/.gitignore

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+ver/*/core.mod
+ver/*/framerate
+ver/*/frames/
+ver/*/jt12.raw
+ver/*/*_game_sdram.v
+ver/*/mem_ports.inc
+ver/*/mist_dump.v
+ver/*/obj_dir/
+ver/*/rom.bin
+ver/*/sdram.old/
+ver/*/sdram_bank*.bin
+ver/*/sdram_bank*.hex
+ver/*/sim_inputs.hex
+ver/*/shim/
+ver/*/test.wav
+ver/*/test.cpp
+ver/*/sdram.cpp
+ver/*/sdram.h
+ver/*/wavewritter.cpp
+ver/*/wavewritter.h

cores/argus/AUTHORS.md

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+# Authors
+
+Core implementation:
+
+- Fulvio Venturelli
+
+JTFRAME/JTCORES reusable infrastructure:
+
+- Jose Tejada Gomez and contributors
+
+Reference emulation:
+
+- MAME Argus driver by Yochizo
+- FinalBurn Neo Argus driver contributors

cores/argus/README.md

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+# Argus Core
+
+FPGA implementation of **Argus** (NMK/Jaleco, 1986), targeting the MiSTer
+platform through JTFRAME. Copyright (C) 2026 Fulvio Venturelli, distributed
+under the GNU General Public License version 3 or later (see
+[LICENSE](../../LICENSE)).
+
+Built on top of Jose Tejada's `jtframe` framework (also GPL-3). This core is
+being brought up from emulator references because no original schematics have
+been found. The implementation is guided by MAME's Jaleco `argus.cpp` /
+`argus_v.cpp` driver, the local MAME-compatible `argus.zip` ROM set, and live
+Verilator comparison against MAME reference frames. See
+[AUTHORS.md](AUTHORS.md) for attribution.
+
+## Status
+
+Supported MAME set for the jtframe config:
+
+- `argus`: **Argus**.
+
+Related MAME sets `valtric`, `butasan`, and `butasanj` share parts of the same
+driver, but they are out of scope for this first hardware pass.
+
+Verilator board simulation currently boots the real `argus` ROM image, transfers
+ROM by frame 12, accepts the repeatable coin/start input script, and reaches the
+title/credit path with recognizable background, logo, text, palette, and sprite
+output.
+
+Current implemented video work includes:
+
+- MAME-described BG0 VROM metadata lookup cached with `jtframe_dual_ram`
+- BG0 palette intensity add/subtract path
+- Jaleco blend-device sprite alpha nibble handling
+- Argus packed-MSB 4bpp tile conversion for BG, text, and sprites
+- 256x224 active timing aligned to the MAME visible area, then rotated by
+  JTFRAME core-mod for the vertical cabinet view
+- live frame viewer inherited from the Operation Wolf/Rainbow Islands workflow
+
+Known issues:
+
+- Ship departing smoke animation is corrupted.
+- Background becomes black after the supernova.
+- Scroll stuttering remains; movement is not yet as smooth as MAME/arcade.
+- Cursor is offset upward on the score name entry screen.
+
+MAME itself marks the Argus driver as imperfect graphics, so each visual fix
+should be checked against a saved MAME frame rather than assumed correct.
+
+## Repo Layout
+
+| Path | What it is |
+|---|---|
+| `hdl/` | Verilog - Argus-specific CPU, video, palette, sprite, and sound glue |
+| `mist/` | Generated MiSTer SDRAM wrapper and memory port includes |
+| `cfg/` | `files.yaml`, `mem.yaml`, `macros.def`, MRA, DIP, and pause text inputs |
+| `doc/` | Local MAME/FBNeo reference snapshots |
+| `ver/argus/` | Verilator sim wrapper and repeatable input script |
+| `tools/` | `framewatch.py`, the live browser frame viewer |
+
+## Reused Blocks
+
+The Argus-specific RTL is intentionally limited to address decoding, BG0 VROM
+lookup, palette/intensity rules, sprite table scanning, and board glue. Reused
+JTFRAME/JTCORES blocks include:
+
+- Z80 CPUs: `jtframe_z80_romwait`
+- YM2203: `jt03`
+- video timing: `jtframe_vtimer`
+- tile layers: `jtframe_scroll`
+- sprite drawing: `jtframe_objdraw`
+- local RAMs: `jtframe_dual_ram` and `jtframe_dual_ram16`
+
+## Building & Simulating
+
+Generate the MRA and ROM payloads from a MAME-compatible `argus.zip`:
+
+```bash
+cd /path/to/jtcores
+JTROOT=$PWD \
+JTFRAME=$PWD/modules/jtframe \
+CORES=$PWD/cores \
+MODULES=$PWD/modules \
+JTBIN=$PWD/release \
+PATH=$PWD/modules/jtframe/bin:$PATH \
+modules/jtframe/bin/jtframe mra argus --setname argus --path /path/to/roms
+```
+
+Expected local outputs:
+
+```text
+release/mra/Argus.mra
+rom/argus.rom
+rom/argus.dip
+rom/argus.mod
+```
+
+The local sim wrapper sets up the JTFRAME environment, refreshes
+`rom/argus.rom`/`rom/argus.mod` when needed, and invokes `jtsim`:
+
+```bash
+cd cores/argus/ver/argus
+ARGUS_ROM=/path/to/roms ./sim.sh -frame 300 -fast
+```
+
+For a repeatable credit/start run:
+
+```bash
+cd cores/argus/ver/argus
+ARGUS_ROM=/path/to/roms ./sim.sh -frame 300 -fast -inputs start_game.cab
+```
+
+For a visual frame capture run:
+
+```bash
+cd cores/argus/ver/argus
+JTFRAME_SIM_VIDEO_EVERY=90 ARGUS_ROM=/path/to/roms ./sim.sh -frame 91 -fast
+```
+
+The live frame viewer can stay open across sim runs:
+
+```bash
+python3 cores/argus/tools/framewatch.py --port 8766
+```
+
+Open `http://127.0.0.1:8766/` and leave it running while the sim writes frames
+under `ver/argus/frames/`.
+
+## Reference Sources
+
+- MAME Jaleco driver: `doc/argus.cpp`
+- MAME Jaleco video driver: `doc/argus_v.cpp`
+- MAME state header: `doc/argus.h`
+- FBNeo reference driver: `doc/fbneo_d_argus.cpp`
+
+Upstream references:
+
+- <https://github.com/mamedev/mame/blob/master/src/mame/jaleco/argus.cpp>
+- <https://github.com/mamedev/mame/blob/master/src/mame/jaleco/argus_v.cpp>
+- <https://github.com/finalburnneo/FBNeo/blob/master/src/burn/drv/pre90s/d_argus.cpp>
+
+## License
+
+GPL-3-or-later. Every HDL file carries its own attribution header where
+applicable. The implementation uses JTFRAME/JTCORES reusable modules by Jose
+Tejada and contributors, plus behavioural details derived from MAME and FBNeo
+reference drivers. See [LICENSE](../../LICENSE) and [AUTHORS.md](AUTHORS.md).

cores/argus/cfg/files.yaml

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+argus:
+  - get:
+    - jtargus_*.v
+jtframe:
+  - get:
+    - jtframe_edge.v
+    - jtframe_sh.v
+  - from: cpu
+    get:
+      - jtframe_z80.yaml
+      - jtframe_z80wait.v
+  - from: ram
+    get:
+      - jtframe_dual_ram.v
+      - jtframe_dual_ram16.v
+      - jtframe_obj_buffer.v
+  - from: video
+    get:
+      - jtframe_vtimer.v
+      - jtframe_scroll.yaml
+      - jtframe_draw.v
+      - jtframe_objdraw.v
+      - jtframe_objdraw_gate.v
+  - from: video/layouts
+    get:
+      - jtframe_8x8x4_packed_msb.v
+jt12:
+  - get:
+    - jt03.yaml

cores/argus/cfg/macros.def

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+[*]
+CORENAME=JTARGUS
+JTFRAME_BUTTONS=2
+JTFRAME_CREDITS_PAGES=1
+
+JTFRAME_VERTICAL
+JTFRAME_WIDTH=256
+JTFRAME_HEIGHT=224
+JTFRAME_PXLCLK=6
+JTFRAME_ARX=5
+JTFRAME_ARY=4
+
+# ROM layout
+JTFRAME_BA1_START=0x30000
+JTFRAME_BA2_START=0x40000
+BG0_START=0x60000
+JTFRAME_BA3_START=0x80000
+TXT_START=0x88000
+VROM1_START=0x90000
+VROM2_START=0x98000

cores/argus/cfg/mame2mra.toml

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+[global]
+overrule=[ {rotate=270} ]
+
+[parse]
+sourcefile=[ "argus.cpp" ]
+main_setnames=[ "argus" ]
+
+[dipsw]
+delete=[
+    { names=["Unused"] },
+]
+
+[buttons]
+names=[
+    { names="Shot 1,Shot 2" }
+]
+
+[ROM]
+regions = [
+    { name="maincpu" },
+    { name="audiocpu", start="JTFRAME_BA1_START" },
+    { name="gfx1",     start="JTFRAME_BA2_START" },
+    { name="gfx2",     start="BG0_START" },
+    { name="gfx3",     start="JTFRAME_BA3_START" },
+    { name="gfx4",     start="TXT_START" },
+    { name="vrom1",    start="VROM1_START" },
+    { name="vrom2",    start="VROM2_START" },
+]
+
+order = [
+    "maincpu", "audiocpu", "gfx1", "gfx2", "gfx3", "gfx4", "vrom1", "vrom2"
+]

cores/argus/cfg/mem.yaml

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+params:
+  - { name: BG0_OFFSET,   value: "(`BG0_START-`JTFRAME_BA2_START)>>1" }
+  - { name: TXT_OFFSET,   value: "(`TXT_START-`JTFRAME_BA3_START)>>1" }
+  - { name: VROM1_OFFSET, value: "(`VROM1_START-`JTFRAME_BA3_START)>>1" }
+  - { name: VROM2_OFFSET, value: "`VROM2_START-`VROM1_START" }
+
+clocks:
+  clk48:
+    - freq: 5M
+      gate: [ "main", "snd" ]
+      outputs:
+        - cen5
+        - cen5b
+    - freq: 1500000
+      outputs:
+        - cen1p5
+        - cen1p5b
+
+audio:
+  rsum: 10k
+  gain: 0.7
+  channels:
+    - { name: fm,  module: jt03_fm,  rsum: 20k, rc: [{ r: 1rout, c: 1.2n }] }
+    - { name: psg, module: jt03_psg, rsum: 60k }
+
+sdram:
+  banks:
+    - buses:
+      - name: main
+        addr_width: 18
+        data_width: 8
+    - buses:
+      - name: snd
+        addr_width: 16
+        data_width: 8
+    - buses:
+      - name: obj
+        addr_width: 17
+        data_width: 32
+      - name: bg0
+        addr_width: 17
+        data_width: 32
+        offset: BG0_OFFSET
+    - buses:
+      - name: bg1
+        addr_width: 15
+        data_width: 32
+      - name: txt
+        addr_width: 15
+        data_width: 32
+        offset: TXT_OFFSET
+      - name: vrom
+        addr_width: 16
+        data_width: 8
+        offset: VROM1_OFFSET

cores/argus/cfg/msg

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+         \BJTARGUS\W
+    FPGA core by Fulvio
+
+  Version \C - \D
+
+       Based on MAME
+          and FBNeo
+
+       Work in progress

cores/argus/cfg/reg.yaml

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+argus: