Argus core vibe coded by Fulvio

[jotego]

@rp-jt review this one too. Look at my notes.

[Copilot]

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[jotego]

changes needed

[jotego]

Change to engineering notation

[jotego]

Need to check with PCB

[jotego]

move to BRAM section in mem.yaml

[jotego]

Do not use arrays, but instantiate jtframe_ram modules instead. This applies to base and spr_blend below too

[jotego]

The style of this file, with so many functions is very unlike the rest of the project.

[jotego]

Do memory decoding like in the other cores

[jotego]

Remove the LUMPED parameter unless there is evidence of the PCB being that way

[jotego]

The core build should have no core-specific warnings either:

Warning (10036): Verilog HDL or VHDL warning at jtargus_game_sdram.v(66): object "sdram_offset_zero" assigned a value but never read File: /home/jtejada/jtcores-2/cores/argus/mister/jtargus_game_sdram.v Line: 66
Warning (10036): Verilog HDL or VHDL warning at jtargus_palette.v(19): object "palram" assigned a value but never read File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_palette.v Line: 19
Warning (10036): Verilog HDL or VHDL warning at jtargus_palette.v(20): object "base" assigned a value but never read File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_palette.v Line: 20
Warning (10036): Verilog HDL or VHDL warning at jtargus_palette.v(22): object "intensity" assigned a value but never read File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_palette.v Line: 22
Warning (10027): Verilog HDL or VHDL warning at the jtargus_palette.v(29): index expression is not wide enough to address all of the elements in the array File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_palette.v Line: 29
Warning (10776): Verilog HDL warning at jtargus_palette.v(93): variable grey in static task or function bg_effect may have unintended latch behavior File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_palette.v Line: 93
Warning (10230): Verilog HDL assignment warning at jtargus_bg0.v(27): truncated value with size 32 to match size of target (20) File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_bg0.v Line: 27
Warning (10036): Verilog HDL or VHDL warning at jtargus_colmix.v(23): object "bg0_opaque" assigned a value but never read File: /home/jtejada/jtcores-2/cores/argus/hdl/jtargus_colmix.v Line: 23

[jotego]

The bottom left chips could be 8x 1-bit SDRAM chips for a frame buffer. That would explain the 1-frame delay. Sadly, it is not possible to read the chip ID from the picture.