ULP-core interrupt handling

esp-lp-hal/CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Added
 - Add `wake_hp_core` for ESP32-S2 and ESP32-S3 (#5133)
 - Add `OutputOpenDrain` GPIO type (#5131)
+- ESP32-S2, ESP32-S3: Added ULP interrupt support (#5206)
 
 ### Changed
 - Changed ULP entrypoint to allow `main()` to return, and halt, to the ULP Timer can be used (#5134)
@@ -18,6 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Fix panic when handling buffers larger than 7 bytes in `LpI2c.write` and `LpI2c.read` (#4694)
 - ESP32-S2, ESP32-S3: Aligned `ulp_riscv_halt()` with ESP_IDF by setting the `cocpu_shut_reset_en` bit, squashing a rare bug where halting the chip would hang (#5134)
+- ESP32-S2, ESP32-S3: Prevent `Peripherals::take().unwrap()` from panicking on second ULP Timer `main()`-loop, by clearing `DEVICE_PERIPHERALS` variable on start (#5206)
 
 ### Removed
 

esp-lp-hal/Cargo.toml

@@ -43,11 +43,13 @@ embedded-io-06    = { package = "embedded-io", version = "0.6",  optional = true
 embedded-io-07    = { package = "embedded-io", version = "0.7",  optional = true }
 nb                = { version = "1.1.0",  optional = true }
 procmacros        = { version = "0.21.0", package = "esp-hal-procmacros", path = "../esp-hal-procmacros" }
-riscv             = { version = "0.15", features = ["critical-section-single-hart"] }
+riscv             = { version = "0.15" }
+portable-atomic = { version = "1", default-features = false }
+critical-section = { version = "1.2.0", features = ["restore-state-u32"], optional = true }
 esp-metadata-generated = { version = "0.3.0", path = "../esp-metadata-generated" }
-esp32c6-lp        = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "fc3e6d4" }
-esp32s2-ulp       = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "fc3e6d4" }
-esp32s3-ulp       = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "fc3e6d4" }
+esp32c6-lp        = { version = "0.3.0", features = ["critical-section"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "5ff8e30e" }
+esp32s2-ulp       = { version = "0.3.0", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "5ff8e30e" }
+esp32s3-ulp       = { version = "0.3.0", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "5ff8e30e" }
 
 [dev-dependencies]
 panic-halt = "0.2.0"
@@ -67,11 +69,11 @@ debug = [
 
 # Chip Support Feature Flags
 # Target the ESP32-C6.
-esp32c6 = ["dep:esp32c6-lp",  "esp-metadata-generated/esp32c6", "procmacros/is-lp-core", "dep:nb"]
+esp32c6 = ["dep:esp32c6-lp",  "esp-metadata-generated/esp32c6", "procmacros/is-lp-core", "dep:nb", "riscv/critical-section-single-hart"]
 # Target the ESP32-S2.
-esp32s2 = ["dep:esp32s2-ulp", "esp-metadata-generated/esp32s2", "procmacros/is-ulp-core"]
+esp32s2 = ["dep:esp32s2-ulp", "esp-metadata-generated/esp32s2", "procmacros/is-ulp-core", "dep:critical-section" ]
 # Target the ESP32-S3.
-esp32s3 = ["dep:esp32s3-ulp", "esp-metadata-generated/esp32s3", "procmacros/is-ulp-core"]
+esp32s3 = ["dep:esp32s3-ulp", "esp-metadata-generated/esp32s3", "procmacros/is-ulp-core", "dep:critical-section" ]
 
 #! ### Trait Implementation Feature Flags
 ## Implement the traits defined in the `1.0.0` releases of `embedded-hal` and
@@ -84,6 +86,10 @@ embedded-io = ["dep:embedded-io-06", "dep:embedded-io-07"]
 name              = "blinky"
 required-features = []
 
+[[example]]
+name              = "interrupt_counter"
+required-features = ["esp32s3"]
+
 [[example]]
 name              = "i2c"
 required-features = ["esp32c6"]

esp-lp-hal/examples/interrupt_counter.rs

@@ -0,0 +1,78 @@
+//! ULP interrupt-based counter example.
+//! Increments a 32 bit counter value at a known point in memory, whenever the ULP program is run.
+//! If GPIO0 is pressed, resets the counter.
+
+//% CHIPS: esp32s3
+
+#![no_std]
+#![no_main]
+
+extern crate panic_halt;
+
+use core::cell::RefCell;
+
+use critical_section::Mutex;
+use esp_lp_hal::{
+    gpio::{Event, Input, Io},
+    interrupt::{self, Interrupt},
+    pac::Peripherals,
+    prelude::*,
+};
+
+const ADDRESS: usize = 0x1000;
+
+static BUTTON: Mutex<RefCell<Option<Input<0>>>> = Mutex::new(RefCell::new(None));
+
+#[entry]
+fn main(mut button: Input<0>) {
+    let peripherals = Peripherals::take().unwrap();
+    let mut io = Io::new(peripherals.RTC_IO);
+    io.set_interrupt_handler(gpio_interrupt_handler);
+
+    critical_section::with(|cs| {
+        button.listen(Event::FallingEdge);
+        BUTTON.borrow_ref_mut(cs).replace(button);
+    });
+
+    interrupt::bind_handler(Interrupt::RISCV_START_INT, startup_interrupt_handler);
+}
+
+#[handler]
+fn startup_interrupt_handler() {
+    // Increment the counter every time RISCV_START_INT is triggered
+    unsafe {
+        let counter = ADDRESS as *mut u32;
+        counter.write_volatile(counter.read_volatile() + 1);
+    }
+
+    // On entry, immediately disable any more start-up interrupts.
+    // This is needed, because RISCV_START_INT is driven from the ULP Timer,
+    // which may be called multiple times before main() has finished execution.
+    interrupt::set_enabled(Interrupt::RISCV_START_INT, false);
+}
+
+#[handler]
+fn gpio_interrupt_handler() {
+    // Check if BUTTON has an interrupt pending
+    if critical_section::with(|cs| {
+        BUTTON
+            .borrow_ref_mut(cs)
+            .as_mut()
+            .unwrap()
+            .is_interrupt_set()
+    }) {
+        // The button was the source of the interrupt, reset the counter to 0.
+        unsafe {
+            let counter = ADDRESS as *mut u32;
+            counter.write_volatile(0);
+        }
+    }
+
+    critical_section::with(|cs| {
+        BUTTON
+            .borrow_ref_mut(cs)
+            .as_mut()
+            .unwrap()
+            .clear_interrupt()
+    });
+}

esp-lp-hal/ld/link-ulp.x

@@ -4,6 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/* Provides interrupt vector symbols */
+INCLUDE device.x
+
 ENTRY(reset_vector)
 
 CONFIG_ULP_COPROC_RESERVE_MEM = 8 * 1024;
@@ -15,39 +18,43 @@ MEMORY
 
 SECTIONS
 {
-    . = ORIGIN(ram);
-
-    .text :
-    {
-        *(.text.vectors) /* Default reset vector must link to offset 0x0 */
-
-        KEEP(*(.init));
-        KEEP(*(.init.rust));         
-        *(.text)
-        *(.text*)
-    } >ram
-
-    .rodata ALIGN(4):
-    {
-        *(.rodata)
-        *(.rodata*)
-    } > ram
-
-    .data ALIGN(4):
-    {
-        *(.data)
-        *(.data*)
-        *(.sdata)
-        *(.sdata*)
-    } > ram
-
-    .bss ALIGN(4) :
-    {
-        *(.bss)
-        *(.bss*)
-        *(.sbss)
-        *(.sbss*)
-    } >ram
-
-    __stack_top = ORIGIN(ram) + LENGTH(ram);
+  . = ORIGIN(ram);
+
+  .text :
+  {
+    /* Power-on-reset must be placed at address 0x0 */
+    KEEP(*(.reset));
+    /* ULP will jump to 0x10 when an interrupt trap occurs */
+    . = ALIGN(0x10);
+    KEEP(*(.trap));
+    KEEP(*(.init));
+    KEEP(*(.init.rust));
+    KEEP(*(.trap.rust));
+    *(.text .text.*)
+  } >ram
+
+  .rodata ALIGN(4):
+  {
+    *(.rodata)
+    *(.rodata*)
+  } >ram
+
+  .data ALIGN(4):
+  {
+    PROVIDE(__global_pointer$ = . + 0x800);
+    *(.data)
+    *(.data*)
+    *(.sdata)
+    *(.sdata*)
+  } >ram
+
+  .bss ALIGN(4):
+  {
+    *(.bss)
+    *(.bss*)
+    *(.sbss)
+    *(.sbss*)
+  } >ram
+
+  __stack_top = ORIGIN(ram) + LENGTH(ram);
 }

esp-lp-hal/src/critical_section.rs

@@ -0,0 +1,17 @@
+use critical_section::RawRestoreState;
+
+use crate::interrupt;
+
+struct UlpCriticalSection;
+critical_section::set_impl!(UlpCriticalSection);
+
+unsafe impl critical_section::Impl for UlpCriticalSection {
+    unsafe fn acquire() -> RawRestoreState {
+        interrupt::disable_cpu_interrupts()
+    }
+
+    unsafe fn release(previous_state: RawRestoreState) {
+        // Only re-enable interrupts if they were enabled before the critical section.
+        interrupt::mask_cpu_interrupts(previous_state);
+    }
+}