ULP-core interrupt handling

esp-hal/CHANGELOG.md

@@ -24,6 +24,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - GPIO: `Input::wait_for_with_options()` allows waking from light sleep while waiting for event (#5551)
 
 ### Changed
+- ESP32-S2, ESP32-S3: Renamed `UlpWakeupSource` to `WakeFromUlpCoreWakeupSource`, to differentiate it from `UlpCoreWakeupSource` (#5206)
 
 - The clock frequency accessor functions no longer need to lock the clock tree (#5461)
 - SPI: `SpiDmaBus` has been merged into `SpiDma`. `with_buffers` now returns `SpiDma` directly, and the buffer-taking transfer methods have been renamed to `read_buffer`, `write_buffer`, `transfer_buffers`, `half_duplex_read_buffer` and `half_duplex_write_buffer` to avoid conflicts with the `SpiBus` trait methods. (#5272)
@@ -102,6 +103,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - A `PsramMode` option has been introduced for ESP32-S3. The default mode is `Auto` which will try to detect if PSRAM works via Octal or Quad SPI and configure it accordingly. (#5334)
 - Add I2S loopback logic to the peripheral driver. (#5349)
 - SPI master: added `min_async_transfer_size` config option to force small transfers to use blocking/CPU driven mode. (#5350)
+- ESP32-S2, ESP32-S3: Add `wakeup_enable()` method to `LowPowerInput` and `LowPowerOutputOpenDrain`, allowing ULP core to be woken up from GPIO. (#5134)
 
 ### Changed
 

esp-hal/src/gpio/lp_io.rs

@@ -30,7 +30,10 @@
 use core::marker::PhantomData;
 
 use super::{InputPin, OutputPin, RtcPin};
-use crate::peripherals::{GPIO, LP_AON, LP_IO};
+use crate::{
+    gpio::WakeEvent,
+    peripherals::{GPIO, LP_AON, LP_IO},
+};
 
 /// A GPIO output pin configured for low power operation
 pub struct LowPowerOutput<'d, const PIN: u8> {
@@ -111,6 +114,14 @@ impl<'d, const PIN: u8> LowPowerInput<'d, PIN> {
             .gpio(PIN as usize)
             .modify(|_, w| w.fun_wpd().bit(enable));
     }
+
+    /// Allows this pin to wakeup the LP core, when LpCoreWakeupSource::Gpio is used.
+    pub fn wakeup_enable(&self, event: Option<WakeEvent>) {
+        let pin_reg = LP_IO::regs().pin(PIN as usize);
+        let wake_en = event.is_some();
+        let int_type = event.map_or(0, |e| e as u8);
+        pin_reg.write(|w| unsafe { w.int_type().bits(int_type).wakeup_enable().bit(wake_en) });
+    }
 }
 
 /// A GPIO open-drain output pin configured for low power operation

esp-hal/src/gpio/rtc_io.rs

@@ -33,7 +33,7 @@ use core::marker::PhantomData;
 
 use super::{InputPin, OutputPin, RtcPin};
 use crate::{
-    gpio::RtcFunction,
+    gpio::{RtcFunction, WakeEvent},
     peripherals::{GPIO, RTC_IO},
 };
 
@@ -85,13 +85,13 @@ impl<'d, const PIN: u8> LowPowerInput<'d, PIN> {
         P: InputPin + RtcPin + 'd,
     {
         pin.rtc_set_config(true, true, RtcFunction::Rtc);
-
         let this = Self {
             phantom: PhantomData,
         };
         this.input_enable(true);
         this.pullup_enable(false);
         this.pulldown_enable(false);
+        // this.wakeup_enable(None);
 
         this
     }
@@ -115,6 +115,23 @@ impl<'d, const PIN: u8> LowPowerInput<'d, PIN> {
             .touch_pad(PIN as usize)
             .modify(|_, w| w.rde().bit(enable));
     }
+
+    /// Allows this pin to wakeup the ULP core, when UlpCoreWakeupSource::Gpio is used.
+    pub fn wakeup_enable(&self, event: Option<WakeEvent>) {
+        let pin_reg_rtc = RTC_IO::regs().pin(PIN as usize);
+        let wake_en = event.is_some();
+        let int_type = event.map_or(0, |e| e as u8);
+
+        #[cfg(esp32s3)]
+        pin_reg_rtc.write(|w| unsafe { w.int_type().bits(int_type).wakeup_enable().bit(wake_en) });
+        #[cfg(esp32s2)]
+        pin_reg_rtc.write(|w| unsafe {
+            w.gpio_pin_int_type()
+                .bits(int_type)
+                .gpio_pin_wakeup_enable()
+                .bit(wake_en)
+        });
+    }
 }
 
 /// A GPIO open-drain output pin configured for low power operation

esp-hal/src/rtc_cntl/sleep/esp32s2.rs

@@ -2,7 +2,7 @@ use super::{
     Ext0WakeupSource,
     Ext1WakeupSource,
     TimerWakeupSource,
-    UlpWakeupSource,
+    WakeFromUlpCoreWakeupSource,
     WakeSource,
     WakeTriggers,
     WakeupLevel,
@@ -74,7 +74,7 @@ pub const RTC_MEM_POWERUP_CYCLES: u8 = OTHER_BLOCKS_POWERUP;
 /// RTC memory wait cycles.
 pub const RTC_MEM_WAIT_CYCLES: u16 = OTHER_BLOCKS_WAIT;
 
-impl WakeSource for UlpWakeupSource {
+impl WakeSource for WakeFromUlpCoreWakeupSource {
     fn apply(
         &self,
         _rtc: &Rtc<'_>,

esp-hal/src/rtc_cntl/sleep/esp32s3.rs

@@ -2,7 +2,7 @@ use super::{
     Ext0WakeupSource,
     Ext1WakeupSource,
     TimerWakeupSource,
-    UlpWakeupSource,
+    WakeFromUlpCoreWakeupSource,
     WakeSource,
     WakeTriggers,
     WakeupLevel,
@@ -82,7 +82,7 @@ pub const RTC_MEM_POWERUP_CYCLES: u8 = OTHER_BLOCKS_POWERUP;
 /// RTC memory wait cycles.
 pub const RTC_MEM_WAIT_CYCLES: u16 = OTHER_BLOCKS_WAIT;
 
-impl WakeSource for UlpWakeupSource {
+impl WakeSource for WakeFromUlpCoreWakeupSource {
     fn apply(
         &self,
         _rtc: &Rtc<'_>,

esp-hal/src/rtc_cntl/sleep/mod.rs

@@ -376,15 +376,15 @@ impl Default for WakeFromLpCoreWakeupSource {
 ///
 /// This wakeup source can be used to wake up from both light and deep sleep.
 #[cfg(any(esp32s2, esp32s3))]
-pub struct UlpWakeupSource {
+pub struct WakeFromUlpCoreWakeupSource {
     wake_on_interrupt: bool,
     wake_on_trap: bool,
     clear_interrupts_on_sleep: bool,
 }
 
 #[cfg(any(esp32s2, esp32s3))]
-impl UlpWakeupSource {
-    /// Create a new instance of `WakeFromUlpWakeupSource`
+impl WakeFromUlpCoreWakeupSource {
+    /// Create a new instance of `WakeFromUlpCoreWakeupSource`
     pub const fn new() -> Self {
         Self {
             wake_on_interrupt: true,
@@ -422,7 +422,7 @@ impl UlpWakeupSource {
 }
 
 #[cfg(any(esp32s2, esp32s3))]
-impl Default for UlpWakeupSource {
+impl Default for WakeFromUlpCoreWakeupSource {
     fn default() -> Self {
         Self::new()
     }

esp-hal/src/soc/esp32c6/lp_core.rs

@@ -26,6 +26,8 @@ use crate::peripherals::{LP_AON, LP_CORE, LP_PERI, LPWR, PMU};
 pub enum LpCoreWakeupSource {
     /// Wakeup source from the HP (High Performance) CPU.
     HpCpu,
+    /// Wakeup source from LP IO interrupt status
+    LpIo,
 }
 
 /// Clock sources for the LP core
@@ -119,6 +121,7 @@ fn ulp_lp_core_run(wakeup_src: LpCoreWakeupSource) {
     // Set wake-up sources
     let src = match wakeup_src {
         LpCoreWakeupSource::HpCpu => 0x01,
+        LpCoreWakeupSource::LpIo => 0x04,
     };
     pmu.lp_cpu_pwr1()
         .modify(|_, w| unsafe { w.lp_cpu_wakeup_en().bits(src) });
@@ -133,5 +136,6 @@ fn ulp_lp_core_run(wakeup_src: LpCoreWakeupSource) {
         LpCoreWakeupSource::HpCpu => {
             pmu.hp_lp_cpu_comm().write(|w| w.hp_trigger_lp().set_bit());
         }
+        LpCoreWakeupSource::LpIo => {}
     }
 }

esp-hal/src/soc/esp32s2/ulp_core.rs

@@ -51,6 +51,8 @@ pub enum UlpCoreWakeupSource {
     /// Wakeup after the ULP Timer has elapsed.
     /// The actual period between wake-ups is affected by the runtime duration of the ULP program.
     Timer(UlpCoreTimerCycles),
+    /// Wakeup on GPIO state
+    Gpio,
 }
 
 /// ULP Timer cycles are clocked at a rate of approximately 8MHz / 32768  = ~244 Hz.
@@ -192,5 +194,10 @@ fn ulp_config_wakeup_source(wakeup_src: UlpCoreWakeupSource) {
             // configure timer duration
             configure_timer(sleep_cycles.cycles());
         }
+        UlpCoreWakeupSource::Gpio => {
+            LPWR::regs()
+                .ulp_cp_timer()
+                .write(|w| w.ulp_cp_gpio_wakeup_ena().set_bit());
+        }
     }
 }

esp-hal/src/soc/esp32s3/ulp_core.rs

@@ -51,6 +51,8 @@ pub enum UlpCoreWakeupSource {
     /// Wakeup after the ULP Timer has elapsed.
     /// The actual period between wake-ups is affected by the runtime duration of the ULP program.
     Timer(UlpCoreTimerCycles),
+    /// Wakeup on GPIO state
+    Gpio,
 }
 
 /// ULP Timer cycles are clocked at a rate of approximately 17.5MHz / 32768  = ~534 Hz.
@@ -103,7 +105,7 @@ impl<'d> UlpCore<'d> {
 
     /// Stops the ULP core.
     pub fn stop(&mut self) {
-        ulp_stop();
+        ulp_halt();
     }
 
     /// Runs the ULP core with the specified wakeup source.
@@ -112,28 +114,61 @@ impl<'d> UlpCore<'d> {
     }
 }
 
-fn ulp_stop() {
+fn ulp_timer_resume() {
+    let rtc_cntl = LPWR::regs();
+    rtc_cntl
+        .ulp_cp_timer()
+        .modify(|_, w| w.ulp_cp_slp_timer_en().set_bit());
+}
+
+fn ulp_timer_stop() {
     let rtc_cntl = LPWR::regs();
     rtc_cntl
         .ulp_cp_timer()
         .modify(|_, w| w.ulp_cp_slp_timer_en().clear_bit());
+}
 
+fn ulp_timer_period(cycles: u32) {
+    let rtc_cntl = LPWR::regs();
+    rtc_cntl
+        .ulp_cp_timer_1()
+        .write(|w| unsafe { w.ulp_cp_timer_slp_cycle().bits(cycles << 8) });
+    rtc_cntl
+        .ulp_cp_ctrl()
+        .modify(|_, w| w.ulp_cp_force_start_top().clear_bit());
+}
+
+fn ulp_halt() {
+    ulp_timer_stop();
+    let rtc_cntl = LPWR::regs();
     // suspends the ulp operation
     rtc_cntl
         .cocpu_ctrl()
         .modify(|_, w| w.cocpu_done().set_bit());
-
     // Resets the processor
     rtc_cntl
         .cocpu_ctrl()
         .modify(|_, w| w.cocpu_shut_reset_en().set_bit());
+}
+
+fn ulp_reset() {
+    let rtc_cntl = LPWR::regs();
+
+    rtc_cntl.cocpu_ctrl().write(|w| {
+        w.cocpu_shut().clear_bit();
+        w.cocpu_done().clear_bit();
+        w.cocpu_shut_reset_en().clear_bit()
+    });
 
     crate::rom::ets_delay_us(20);
 
-    // above doesn't seem to halt the ULP core - this will
-    rtc_cntl
-        .cocpu_ctrl()
-        .modify(|_, w| w.cocpu_clkgate_en().clear_bit());
+    rtc_cntl.cocpu_ctrl().write(|w| {
+        w.cocpu_shut().set_bit();
+        w.cocpu_done().set_bit();
+        w.cocpu_shut_reset_en().set_bit()
+    });
+
+    crate::rom::ets_delay_us(20);
 }
 
 fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
@@ -194,34 +229,26 @@ fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
             .ulp_cp()
             .clear_bit_by_one()
     });
-
-    rtc_cntl
-        .cocpu_ctrl()
-        .modify(|_, w| w.cocpu_clkgate_en().set_bit());
 }
 
 fn ulp_config_wakeup_source(wakeup_src: UlpCoreWakeupSource) {
     // ESP-IDF source: https://github.com/espressif/esp-idf/blob/12f36a021f511cd4de41d3fffff146c5336ac1e7/components/ulp/ulp_riscv/ulp_riscv.c#L87
-    fn configure_timer(cycles: u32) {
-        LPWR::regs()
-            .ulp_cp_timer_1()
-            .write(|w| unsafe { w.ulp_cp_timer_slp_cycle().bits(cycles << 8) });
-        // enable the timer
-        LPWR::regs()
-            .ulp_cp_ctrl()
-            .modify(|_, w| w.ulp_cp_force_start_top().clear_bit());
-        LPWR::regs()
-            .ulp_cp_timer()
-            .modify(|_, w| w.ulp_cp_slp_timer_en().set_bit());
-    }
+
     match wakeup_src {
         UlpCoreWakeupSource::HpCpu => {
             // wake-up immediately
-            configure_timer(0);
+            ulp_timer_period(0);
+            ulp_timer_resume();
         }
         UlpCoreWakeupSource::Timer(sleep_cycles) => {
             // configure timer duration
-            configure_timer(sleep_cycles.cycles());
+            ulp_timer_period(sleep_cycles.cycles());
+            ulp_timer_resume();
+        }
+        UlpCoreWakeupSource::Gpio => {
+            LPWR::regs()
+                .ulp_cp_timer()
+                .write(|w| w.ulp_cp_gpio_wakeup_ena().set_bit());
         }
     }
 }

esp-lp-hal/CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ### Added
 - Add `wake_hp_core` for ESP32-S2 and ESP32-S3 (#5133)
 - Add `OutputOpenDrain` GPIO type (#5131)
+- ESP32-S2, ESP32-S3: Added ULP interrupt support (#5206)
 
 ### Changed
 - Changed ULP entrypoint to allow `main()` to return, and halt, to the ULP Timer can be used (#5134)
@@ -18,6 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Fix panic when handling buffers larger than 7 bytes in `LpI2c.write` and `LpI2c.read` (#4694)
 - ESP32-S2, ESP32-S3: Aligned `ulp_riscv_halt()` with ESP_IDF by setting the `cocpu_shut_reset_en` bit, squashing a rare bug where halting the chip would hang (#5134)
+- ESP32-S2, ESP32-S3: Prevent `Peripherals::take().unwrap()` from panicking on second ULP Timer `main()`-loop, by clearing `DEVICE_PERIPHERALS` variable on start (#5206)
 
 ### Removed