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soc/core/gpio: Add per bit oe to GPIOTristate #393

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soc/core/gpio: Add per bit oe to GPIOTristate #393

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18 changes: 18 additions & 0 deletions litex/soc/cores/gpio.py
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Original file line number Diff line number Diff line change
Expand Up @@ -43,3 +43,21 @@ def __init__(self, pads):
self.comb += t.oe.eq(self._oe.storage)
self.comb += t.o.eq(self._out.storage)
self.specials += MultiReg(t.i, self._in.status)

# GPIO Bidirectional -------------------------------------------------------------------------------

class GPIOBidirectional(Module, AutoCSR):
def __init__(self, pads):
self._pins_in = CSRStatus(len(pads))
self._pins_out = CSRStorage(len(pads))
self._pins_oe = CSRStorage(len(pads))
gpio_pins_t = [None] * len(pads)
bit = 0
for pin_group in pads.layout:
for pin in getattr(pads, pin_group[0]):
gpio_pins_t[bit] = TSTriple()
self.specials += gpio_pins_t[bit].get_tristate(pin)
self.comb += gpio_pins_t[bit].o.eq(self._pins_out.storage[bit])
self.comb += gpio_pins_t[bit].oe.eq(self._pins_oe.storage[bit])
self.comb += self._pins_in.status[bit].eq(gpio_pins_t[bit].i)
bit=bit+1