soc/core/gpio: Add per bit oe to GPIOTristate

[TomKeddie]

I've been finding this class very useful so I thought I'd try upstreaming it.

[TomKeddie]

Actually this is better done as a variant of GPIOTristate that adds per bit tristate control. Will rework.

[enjoy-digital]

@TomKeddie: thanks. I was just looking at the code and trying to understand the difference with GPIOTristate.

[TomKeddie]

@enjoy-digital thanks for your patience, I wrote GPIOBidirectional back in August and totally missed when you added GPIOTristate in Dec.

I'm trying to use GPIOTristate and I don't see what arguments I should pass to make get_tristate() happy with a record.

        self.submodules.j2 = GPIOTristate(platform.request("j2"))

gives me an error from the list being the wrong type

Traceback (most recent call last):
  File "gpio.py", line 244, in <module>
    main()
  File "gpio.py", line 238, in main
    soc = BaseSoC(args.revision, **soc_core_argdict(args))
  File "gpio.py", line 174, in __init__
    self.submodules.j2 = GPIOTristate(platform.request("j2"))
  File "/home/tom/git/TomKeddie/prj-litex/colorlight-5a-75b/gpio/litex/litex/soc/cores/gpio.py", line 42, in __init__
    self.specials += t.get_tristate(pads)
  File "/home/tom/git/TomKeddie/prj-litex/colorlight-5a-75b/gpio/migen/migen/fhdl/specials.py", line 122, in get_tristate
    return Tristate(target, self.o, self.oe, self.i)
  File "/home/tom/git/TomKeddie/prj-litex/colorlight-5a-75b/gpio/migen/migen/fhdl/specials.py", line 57, in __init__
    self.target = wrap(target)
  File "/home/tom/git/TomKeddie/prj-litex/colorlight-5a-75b/gpio/migen/migen/fhdl/structure.py", line 161, in wrap
    .format(value, type(value)))
TypeError: Object '<Record R0:G0:B0:R1:G1:B1:A:B at 0x7f06b65929d0>' of type <class 'migen.genlib.record.Record'> is not a Migen value

So I flattened the list and Cated it.

        self.submodules.j2 = GPIOTristate(Cat(platform.request("j2").flatten()))

and I get what might be bad verilog.

/home/tom/git/TomKeddie/prj-litex/colorlight-5a-75b/gpio/soc_basesoc_colorlight_5a_75b/gateware/top.v:1965: ERROR: syntax error, unexpected '['

Is this user error? or something to log in an issue?

TRELLIS_IO #(
	.DIR("BIDIR")
) TRELLIS_IO (
	.B({j2_B, j2_A, j2_B1, j2_G1, j2_R1, j2_B0, j2_G0, j2_R0}[0]),
	.I(j2_o[0]),
	.T((~j2_oe)),
	.O(j2_i[0])
);

TRELLIS_IO #(
	.DIR("BIDIR")
) TRELLIS_IO_1 (
	.B({j2_B, j2_A, j2_B1, j2_G1, j2_R1, j2_B0, j2_G0, j2_R0}[1]),
	.I(j2_o[1]),
	.T((~j2_oe)),
	.O(j2_i[1])
);

[TomKeddie]

m-labs/migen#205

[enjoy-digital]

@TomKeddie: thanks for the feedback and Migen PR. For now i implemented with a7c5dd5 a solution that is closer to your original one. This has been tested with:

from litex.soc.cores.gpio import GPIOTristate
self.submodules.gpio_tristate = GPIOTristate(Cat(
    platform.request("user_led", 0),
    platform.request("user_led", 1),
    platform.request("user_led", 2),
    platform.request("user_led", 3),
))
self.add_csr("gpio_tristate")

We'll make use of m-labs/migen#205 if it gets merged.