add support for AD3532R/AD3532 DAC#3177
Conversation
|
Same as #3191, if you are upstreaming, please target branches in sync with upstream cycle (the mirror_ci branches), this helps to avoid using deprecated methods. |
6b805e2 to
45351b7
Compare
|
v2:
|
71cdaf3 to
4b97d37
Compare
|
Please, don't include the CI/CD commit on your pr. |
c87d572 to
0579d93
Compare
LLM reviewThis series adds support for the AD3532R/AD3532 (16-channel) DAC to the existing ad3530r driver, along with a new run: ci/local
|
e196cfc to
fdad854
Compare
1719553 to
55ab0e3
Compare
e27e229 to
631dc05
Compare
|
v4
|
|
there seems to be a CI issue that's why it's failing |
LLM reviewThis series adds support for the AD3532R/AD3532 16-channel DAC to the existing run: 25798407816
|
LLM reviewThis series adds support for the AD3532R/AD3532 16-channel DAC to the existing ad3530r driver, adds the run: 25798530886
|
|
v5
|
|
Hi, just following up on this PR, are there any changes still needed, or is this good to go upstream? It seems CI failing are unrelated to this PR. |
Add a new powerdown mode for DACs with 10kohm resistor to GND. Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
The AD3532R/AD3532 is a 16-channel version of the AD3530R/AD3530. This adds compatible strings for the AD3532R/AD3532. Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
The AD3532R/AD3532 is a 16-channel, 16-bit voltage output DAC with a dual-bank register architecture (bank 0 at 0x1000 for channels 0-7, bank 1 at 0x3000 for channels 8-15). Introduce a table-driven register bank approach: per-chip register address arrays in chip_info are iterated by ad3530r_update_reg_banks() and ad3530r_write_reg_banks() helpers. This replaces the single-register setup calls for existing variants (AD3530R, AD3531R) and scales naturally to the AD3532R's dual-bank layout without per-variant conditionals in the setup path. Convert sw_ldac_trig_reg from a static register address to a function pointer to handle the AD3532R's per-bank LDAC trigger registers. Add AD3532R-specific powerdown modes (1kohm_to_gnd, 10kohm_to_gnd, three_state) matching the OUTPUT_OPERATING_MODE register encoding, and a dedicated ad3532r_set_dac_powerdown() using arithmetic channel-to- register mapping for the 16-channel address space. Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
PR Description
Add support for the AD3532R/AD3532 16-channel, 16-bit voltage output DAC.
These devices use a dual-bank register architecture with base addresses at
0x1000 (bank 0) and 0x3000 (bank 1). Channels 0-7 are mapped to bank 0,
while channels 8-15 are mapped to bank 1.
Key Changes:
ad3532r_input_ch_reg()andad3532r_trigger_sw_ldac_reg()forbank-aware register addressing
sw_ldac_trig_regfrom a static register value to a per-variantfunction pointer to support bank-dependent SW LDAC triggering
ad3532r_set_dac_powerdown()to handle the 4-register powerdownmapping across both banks
ad3530r_normal_op_mode()and extendad3530r_setup()toconfigure dual-bank software reset, output range, and reference control
PR Type
PR Checklist