SequentialPlacer takes into account max channels per tile

include/aie-c/TargetModel.h

@@ -140,6 +140,18 @@ aieTargetModelGetMemTileSize(AieTargetModel targetModel);
 MLIR_CAPI_EXPORTED uint32_t
 aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row);
 
+MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetNumDestSwitchboxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle);
+
+MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetNumSourceSwitchboxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle);
+
+MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetNumDestShimMuxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle);
+
+MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetNumSourceShimMuxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle);
+
 /// Returns true if this is an NPU target model.
 MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel);
 

lib/CAPI/TargetModel.cpp

@@ -154,6 +154,38 @@ uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col,
   return unwrap(targetModel).getNumBanks(col, row);
 }
 
+uint32_t aieTargetModelGetNumDestSwitchboxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle) {
+  xilinx::AIE::WireBundle wireBundle =
+      static_cast<xilinx::AIE::WireBundle>(bundle);
+  return unwrap(targetModel)
+      .getNumDestSwitchboxConnections(col, row, wireBundle);
+}
+
+uint32_t aieTargetModelGetNumSourceSwitchboxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle) {
+  xilinx::AIE::WireBundle wireBundle =
+      static_cast<xilinx::AIE::WireBundle>(bundle);
+  return unwrap(targetModel)
+      .getNumSourceSwitchboxConnections(col, row, wireBundle);
+}
+
+uint32_t aieTargetModelGetNumDestShimMuxConnections(AieTargetModel targetModel,
+                                                    int col, int row,
+                                                    uint32_t bundle) {
+  xilinx::AIE::WireBundle wireBundle =
+      static_cast<xilinx::AIE::WireBundle>(bundle);
+  return unwrap(targetModel).getNumDestShimMuxConnections(col, row, wireBundle);
+}
+
+uint32_t aieTargetModelGetNumSourceShimMuxConnections(
+    AieTargetModel targetModel, int col, int row, uint32_t bundle) {
+  xilinx::AIE::WireBundle wireBundle =
+      static_cast<xilinx::AIE::WireBundle>(bundle);
+  return unwrap(targetModel)
+      .getNumSourceShimMuxConnections(col, row, wireBundle);
+}
+
 bool aieTargetModelIsNPU(AieTargetModel targetModel) {
   return unwrap(targetModel).hasProperty(xilinx::AIE::AIETargetModel::IsNPU);
 }

python/AIEMLIRModule.cpp

@@ -311,10 +311,26 @@ NB_MODULE(_aie, m) {
            [](PyAieTargetModel &self) {
              return aieTargetModelGetMemTileSize(self.get());
            })
-      // .def("get_num_dest_switchbox_connections", int col, int row)
-      // .def("get_num_source_switchbox_connections", int col, int row)
-      // .def("get_num_dest_shim_mux_connections", int col, int row)
-      // .def("get_num_source_shim_mux_connections", int col, int row)
+      .def("get_num_dest_switchbox_connections",
+           [](PyAieTargetModel &self, int col, int row, uint32_t bundle) {
+             return aieTargetModelGetNumDestSwitchboxConnections(
+                 self.get(), col, row, bundle);
+           })
+      .def("get_num_source_switchbox_connections",
+           [](PyAieTargetModel &self, int col, int row, uint32_t bundle) {
+             return aieTargetModelGetNumSourceSwitchboxConnections(
+                 self.get(), col, row, bundle);
+           })
+      .def("get_num_dest_shim_mux_connections",
+           [](PyAieTargetModel &self, int col, int row, uint32_t bundle) {
+             return aieTargetModelGetNumDestShimMuxConnections(self.get(), col,
+                                                               row, bundle);
+           })
+      .def("get_num_source_shim_mux_connections",
+           [](PyAieTargetModel &self, int col, int row, uint32_t bundle) {
+             return aieTargetModelGetNumSourceShimMuxConnections(
+                 self.get(), col, row, bundle);
+           })
       // .def("is_legal_memtile_connection")
       .def("is_npu",
            [](PyAieTargetModel &self) {

python/iron/dataflow/__init__.py

@@ -1 +1 @@
-from .objectfifo import ObjectFifo, ObjectFifoHandle
+from .objectfifo import ObjectFifo, ObjectFifoHandle, ObjectFifoLink, ObjectFifoEndpoint

python/iron/device/device.py

@@ -8,6 +8,7 @@
 
 from abc import abstractmethod
 from ... import ir  # type: ignore
+from ...dialects._aie_enum_gen import WireBundle  # type: ignore
 from ...dialects.aie import AIEDevice, tile, TileOp, get_target_model  # type: ignore
 from ..resolvable import Resolvable
 from .tile import Tile
@@ -116,6 +117,42 @@ def get_compute_tiles(self) -> list[Tile]:
         # TODO: should this be shaped?
         ...
 
+    @abstractmethod
+    def get_num_source_switchbox_connections(self, t: Tile) -> int:
+        """Returns number of DMA source ports in the switchbox for the given tile on the device.
+
+        Returns:
+            int: Number of DMA source ports.
+        """
+        ...
+
+    @abstractmethod
+    def get_num_dest_switchbox_connections(self, t: Tile) -> int:
+        """Returns number of DMA dest ports in the switchbox for the given tile on the device.
+
+        Returns:
+            int: Number of DMA dest ports.
+        """
+        ...
+
+    @abstractmethod
+    def get_num_source_shim_mux_connections(self, t: Tile) -> int:
+        """Returns number of DMA source ports in the shim mux for the given tile on the device.
+
+        Returns:
+            int: Number of DMA source ports.
+        """
+        ...
+
+    @abstractmethod
+    def get_num_dest_shim_mux_connections(self, t: Tile) -> int:
+        """Returns number of DMA dest ports in the shim mux for the given tile on the device.
+
+        Returns:
+            int: Number of DMA dest ports.
+        """
+        ...
+
     def resolve_tile(
         self,
         tile: Tile,
@@ -164,6 +201,49 @@ def get_compute_tiles(self) -> list[Tile]:
                 compute_tiles.append(Tile(col, row))
         return compute_tiles
 
+    def get_num_source_switchbox_connections(self, t: Tile) -> int:
+        col = t.col
+        row = t.row
+        bundle = WireBundle.DMA
+        return get_target_model(self._device).get_num_source_switchbox_connections(
+            col, row, bundle
+        )
+
+    def get_num_dest_switchbox_connections(self, t: Tile) -> int:
+        col = t.col
+        row = t.row
+        bundle = WireBundle.DMA
+        return get_target_model(self._device).get_num_dest_switchbox_connections(
+            col, row, bundle
+        )
+
+    def get_num_source_shim_mux_connections(self, t: Tile) -> int:
+        col = t.col
+        row = t.row
+        bundle = WireBundle.DMA
+        return get_target_model(self._device).get_num_source_shim_mux_connections(
+            col, row, bundle
+        )
+
+    def get_num_dest_shim_mux_connections(self, t: Tile) -> int:
+        col = t.col
+        row = t.row
+        bundle = WireBundle.DMA
+        return get_target_model(self._device).get_num_dest_shim_mux_connections(
+            col, row, bundle
+        )
+
+    def get_num_connections(self, tile: Tile, output: bool) -> int:
+        if tile.row == 0:
+            if output:
+                return self.get_num_source_shim_mux_connections(tile)
+            else:
+                return self.get_num_dest_shim_mux_connections(tile)
+        if output:
+            return self.get_num_source_switchbox_connections(tile)
+        else:
+            return self.get_num_dest_switchbox_connections(tile)
+
 
 def create_class(class_name, device):