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Use native 8-bit PTX atomic loads and stores. #10784

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Merged
griwes merged 1 commit into from
Aug 13, 2026
Merged

Use native 8-bit PTX atomic loads and stores. #10784

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2 changes: 1 addition & 1 deletion libcudacxx/codegen/generators/definitions.h
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Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,7 @@ inline std::string constraints(Operand op, size_t sz)
}},
};

if (sz == 16)
if (sz <= 16)
{
return {"h"};
}
Expand Down
49 changes: 48 additions & 1 deletion libcudacxx/codegen/generators/ld_st.h
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Expand Up @@ -97,8 +97,18 @@ template <class _Type>
static inline _CCCL_DEVICE void __cuda_atomic_load(
const _Type* __ptr, _Type& __dst, {3}, __atomic_cuda_operand_{0}{1}, {5}, {7})
{{ asm volatile("ld{8}{4}{6}.{0}{1} %0,[%1];" : "={2}"(__dst) : "l"(__ptr) : "memory"); }})XXX";
constexpr auto asm_intrinsic_format_8 = R"XXX(
template <class _Type>
static inline _CCCL_DEVICE void __cuda_atomic_load(
const _Type* __ptr, _Type& __dst, {3}, __atomic_cuda_operand_{0}{1}, {5}, {7})
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{{
uint16_t __tmp;
asm volatile("ld{8}{4}{6}.{0}{1} %0,[%1];" : "={2}"(__tmp) : "l"(__ptr) : "memory");
__dst = static_cast<_Type>(__tmp);
}})XXX";

constexpr size_t supported_sizes[] = {
8,
16,
32,
64,
Expand Down Expand Up @@ -140,7 +150,7 @@ static inline _CCCL_DEVICE void __cuda_atomic_load(
{
for (auto mm : mmio_states)
{
if (size == 16 && type == Operand::Floating)
if (size <= 16 && type == Operand::Floating)
{
continue;
}
Expand All @@ -167,6 +177,20 @@ static inline _CCCL_DEVICE void __cuda_atomic_load(
/* 7 */ mmio_tag(mm),
/* 8 */ mmio(mm));
}
else if (size == 8)
{
out << std::format(
asm_intrinsic_format_8,
/* 0 */ operand(type),
/* 1 */ size,
/* 2 */ constraints(type, size),
/* 3 */ semantic_tag(sem),
/* 4 */ semantic_ld_st(sem),
/* 5 */ scope_tag(sco),
/* 6 */ scope_ld_st(sem, sco),
/* 7 */ mmio_tag(mm),
/* 8 */ mmio(mm));
}
else
{
out << std::format(
Expand Down Expand Up @@ -281,8 +305,17 @@ template <class _Type>
static inline _CCCL_DEVICE void __cuda_atomic_store(
_Type* __ptr, _Type& __val, {3}, __atomic_cuda_operand_{0}{1}, {5}, {7})
{{ asm volatile("st{8}{4}{6}.{0}{1} [%0],%1;" :: "l"(__ptr), "{2}"(__val) : "memory"); }})XXX";
constexpr auto asm_intrinsic_format_8 = R"XXX(
template <class _Type>
static inline _CCCL_DEVICE void __cuda_atomic_store(
_Type* __ptr, _Type& __val, {3}, __atomic_cuda_operand_{0}{1}, {5}, {7})
{{
const uint16_t __tmp = static_cast<uint16_t>(__val);
asm volatile("st{8}{4}{6}.{0}{1} [%0],%1;" :: "l"(__ptr), "{2}"(__tmp) : "memory");
}})XXX";

constexpr size_t supported_sizes[] = {
8,
16,
32,
64,
Expand Down Expand Up @@ -348,6 +381,20 @@ static inline _CCCL_DEVICE void __cuda_atomic_store(
/* 7 */ mmio_tag(mm),
/* 8 */ mmio(mm));
}
else if (size == 8)
{
out << std::format(
asm_intrinsic_format_8,
/* 0 */ operand(type),
/* 1 */ size,
/* 2 */ constraints(type, size),
/* 3 */ semantic_tag(sem),
/* 4 */ semantic_ld_st(sem),
/* 5 */ scope_tag(sco),
/* 6 */ scope_ld_st(sem, sco),
/* 7 */ mmio_tag(mm),
/* 8 */ mmio(mm));
}
else
{
out << std::format(
Expand Down
33 changes: 0 additions & 33 deletions libcudacxx/include/cuda/std/__atomic/functions/cuda_ptx_derived.h
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Original file line number Diff line number Diff line change
Expand Up @@ -44,26 +44,6 @@ using __cuda_atomic_enable_non_native_bitwise = enable_if_t<_Operand::__size <=
template <class _Operand>
using __cuda_atomic_enable_native_bitwise = enable_if_t<_Operand::__size >= 32, bool>;

template <class _Operand>
using __cuda_atomic_enable_non_native_ld_st = enable_if_t<_Operand::__size <= 8, bool>;

template <class _Operand>
using __cuda_atomic_enable_native_ld_st = enable_if_t<_Operand::__size >= 16, bool>;

template <class _Type, class _Order, class _Operand, class _Sco, __cuda_atomic_enable_non_native_ld_st<_Operand> = 0>
_CCCL_DEVICE static void
__cuda_atomic_load(const _Type* __ptr, _Type& __dst, _Order, _Operand, _Sco, __atomic_cuda_mmio_disable)
{
constexpr uint64_t __alignmask = (sizeof(uint16_t) - 1);
uint16_t* __aligned = (uint16_t*) ((intptr_t) __ptr & (~__alignmask)); // NOLINT(performance-no-int-to-ptr)
const uint8_t __offset = uint16_t((intptr_t) __ptr & __alignmask) * 8;

uint16_t __value = 0;
__cuda_atomic_load(__aligned, __value, _Order{}, __atomic_cuda_operand_b16{}, _Sco{}, __atomic_cuda_mmio_disable{});

__dst = static_cast<_Type>(__value >> __offset);
}

template <class _Type, class _Order, class _Operand, class _Sco, __cuda_atomic_enable_non_native_bitwise<_Operand> = 0>
_CCCL_DEVICE static bool
__cuda_atomic_compare_exchange(_Type* __ptr, _Type& __dst, _Type __cmp, _Type __op, _Order, _Operand, _Sco)
Expand Down Expand Up @@ -212,19 +192,6 @@ _CCCL_DEVICE_API _Type __cuda_atomic_fetch_update(_Type* __ptr, const _Fn& __op,
return __expected;
}

template <class _Type, class _Order, class _Operand, class _Sco, __cuda_atomic_enable_non_native_ld_st<_Operand> = 0>
_CCCL_DEVICE static void
__cuda_atomic_store(_Type* __ptr, _Type __val, _Order, _Operand, _Sco, __atomic_cuda_mmio_disable)
{
// Store requires cas on 8/16b types
__cuda_atomic_fetch_update(
__ptr,
__cuda_atomic_op_bind<_Type, ::cuda::std::__cuda_atomic_op_store>{__val},
_Order{},
__atomic_cuda_operand_tag<__atomic_cuda_operand::_b, _Operand::__size>{},
_Sco{});
}

template <class _Type, class _Order, class _Operand, class _Sco, __cuda_atomic_enable_non_native_arithmetic<_Operand> = 0>
_CCCL_DEVICE static void __cuda_atomic_fetch_add(_Type* __ptr, _Type& __dst, _Type __op, _Order, _Operand, _Sco)
{
Expand Down
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