Rewritten Parser and Language Services in Rust: Supports Verilog, VHDL, and SystemVerilog with faster performance and more stable services.
- Brand New Netlist Renderer
- Added comprehensive support for VHDL & SV (file tree, LSP, etc.)
- Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, and VVP.
- Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting
function.lsp.linter.vhdl.diagnostor(for VHDL) andfunction.lsp.linter.vlog.diagnostor(for Verilog). - Added LSP and syntax highlighting support for scripts like TCL, XDC, and VVP.
- Display the plugin's working status in the status bar at the bottom of VSCode, making it easier for users to understand the current settings.
- Optimized project configuration directory.
- Improved auto-completion performance.
- Fixed a bug in the Icarus Verilog simulation feature where duplicate paths were included as compilation parameters.
- Fixed a bug in the Icarus Verilog simulation feature where adding or removing
includewould cause simulation compilation to fail (theinstModPathStatusproperty of the instance was not updated). - Fixed simulation issues with Icarus Verilog version 12
- Fixed the issue of being unable to import Block Design (BD) during Vivado project generation
- Fixed the issue where libraries in custom mode could not be imported into Vivado
- Fixed other known bugs.