package.nls.json

{
    "digital-ide.property-json.generate.title": "Generate property.json",
    "digital-ide.property-json.overwrite.title": "Update property.json fields",
    "digital-ide.tool.instance.title": "Generate instance template from selected module",
    "digital-ide.tool.simulateFile.title": "Simulate current module",
    "digital-ide.tool.icarus.simulateFile.title": "Do simulation for current module",
    "digital-ide.treeView.arch.expand.title": "Expand all the items in tree view",
    "digital-ide.treeView.arch.collapse.title": "Collapse all the items in tree view",
    "digital-ide.treeView.arch.refresh.title": "Refresh the tree view",
    "digital-ide.treeView.arch.openFile.title": "Open the corresponding file in tree view",
    "digital-ide.tool.clean.title": "Clean the current project",
    "digital-ide.soft.launch.title": "Launch SDK development assist function",
    "digital-ide.soft.build.title": "Build the current SDK project",
    "digital-ide.soft.download.title": "Download the boot file into the device",
    "digital-ide.soft.selectElf.title": "Select Xilinx processor ELF",
    "digital-ide.soft.reset.title": "Reset Xilinx processor",
    "digital-ide.soft.halt.title": "Halt Xilinx processor",
    "digital-ide.soft.run.title": "Run Xilinx processor",
    "digital-ide.soft.stop.title": "Stop Xilinx processor",
    "digital-ide.soft.status.title": "Read Xilinx processor status",
    "digital-ide.soft.gdb.start.title": "Start Xilinx PS GDB server",
    "digital-ide.soft.gdb.generateConfig.title": "Generate Xilinx PS GDB configuration",
    "digital-ide.soft.gdb.stop.title": "Stop managed Xilinx PS GDB server",
    "digital-ide.hard.launch.title": "Launch FPGA development assist function",
    "digital-ide.hard.simulate.title": "Launch the manufacturer Simulation",
    "digital-ide.hard.simulate.cli.title": "Launch the manufacturer Simulation in CLI",
    "digital-ide.hard.simulate.gui.title": "Launch the manufacturer Simulation in GUI",
    "digital-ide.hard.refresh.title": "Refresh the current project file",
    "digital-ide.hard.build.title": "Build the current fpga project",
    "digital-ide.hard.build.synth.title": "Synth the current project",
    "digital-ide.hard.build.impl.title": "Impl the current project",
    "digital-ide.hard.build.bitstream.title": "Generate the BIT File",
    "digital-ide.hard.program.title": "Download the bit file into the device",
    "digital-ide.hard.program.sram.title": "Program FPGA SRAM",
    "digital-ide.hard.program.flash.title": "Program FPGA Flash",
    "digital-ide.hard.gui.title": "Open the GUI",
    "digital-ide.hard.exit.title": "Exit the current project",
    "digital-ide.pickLibrary.title": "Select lib from custom & common",
    "digital-ide.pl.setSrcTop.title": "Set as top file of src",
    "digital-ide.pl.setSimTop.title": "Set as top file of sim",
    "digital-ide.pl.addFile.title": "Add file",
    "digital-ide.pl.delFile.title": "Del file",
    "digital-ide.netlist.title": "Netlist",
    "digital-ide.lsp.tool.insertTextToUri.title": "Insert text to uri",
    "digital-ide.lsp.tool.transformOldPropertyFile.title": "Transform configure file from previous version to new version",
    "digital-ide.netlist.show.title": "Show netlist of current file",
    "digital-ide.tool.import-filelist.title": "import filelist",
    "digital-ide.tool.export-filelist.title": "export filelist",
    "digital-ide.treeview": "Digital IDE: TreeView",
    "digital-ide.welcome.show.title": "Show welcome text in Digital-IDE",
    "digital-ide.dont-show-again.propose.issue.title": "Show welcome text in Digital-IDE",
    "digital-ide.lib.custom.path.title": "Path of the user-defined lib directory",
    "digital-ide.prj.file.structure.notice.title": "Show a notice when a local file is deleted",
    "digital-ide.prj.vivado.install.path.title": "Set the Xilinx Vivado installation path. For example: D:/APP/vivado_18_3/Vivado/2018.3/bin. The default path is C:/Xilinx/Vivado/2018.3/bin\nIgnore this setting if you add a relative path to the environment variable PATH",
    "digital-ide.prj.efinix.package.path.title": "Set the self-contained Efinity package directory",
    "digital-ide.efinity.install.path.title": "Original Efinity installation root containing bin/efx_run. This is separate from the self-contained package directory.",
    "digital-ide.prj.modelsim.install.path.title": "Set the Modelsim installation path. The default path is C:/modeltech64_10.4/win64\nIgnore this setting if you add a relative path to the environment variable PATH",
    "digital-ide.prj.iverilog.install.path.title": "Installation directory containing the iverilog and vvp executables. Leave empty to resolve both commands from PATH.",
    "digital-ide.prj.xilinx.IP.repo.path.title": "Path of the user-designed Xilinx IP library. After configuring this property, the plugin will automatically add the path to the Vivado IP library.",
    "digital-ide.prj.xilinx.BD.repo.path.title": "User-defined placement path for Xilinx BD files",
    "digital-ide.prj.xsdk.install.path.title": "Set the Xilinx XSCT/Vitis installation path or the xsct executable path",
    "digital-ide.xilinx.ps.hwServer.path.title": "Path to the Xilinx hw_server executable. Leave empty to infer it from XSCT.",
    "digital-ide.xilinx.ps.hwServer.host.title": "Host name or IP address of the Xilinx hw_server.",
    "digital-ide.xilinx.ps.hwServer.port.title": "TCP control port used by the Xilinx hw_server.",
    "digital-ide.xilinx.ps.gdb.portBase.title": "Base port for Xilinx GDB servers: ARM, ARM64, MicroBlaze and MicroBlaze64 use consecutive ports.",
    "digital-ide.xilinx.ps.gdb.arm.path.title": "Path to arm-none-eabi-gdb for Zynq-7000 processors.",
    "digital-ide.xilinx.ps.gdb.aarch64.path.title": "Path to aarch64-none-elf-gdb for ZynqMP Cortex-A53 processors.",
    "digital-ide.xilinx.ps.gdb.armR5.path.title": "Path to armr5-none-eabi-gdb for ZynqMP Cortex-R5 processors.",
    "digital-ide.xilinx.ps.gdb.microblaze.path.title": "Path to microblaze-xilinx-elf-gdb.",
    "digital-ide.xilinx.ps.gdb.microblaze64.path.title": "Path to mb64-gdb for 64-bit MicroBlaze processors.",
    "digital-ide.function.simulate.simulationHome.title": "Legacy simulation output path; unified simulations use prj/simulation/<backend>/<top>",
    "digital-ide.function.simulate.fastSimulator.title": "Fast simulator used by the unified command for Verilog and SystemVerilog. VHDL continues to use ModelSim.",
    "digital-ide.function.simulate.gtkwavePath.title": "Absolute path of the launch path of the gtkwave software",
    "digital-ide.function.simulate.xilinxLibPath.title": "Path of the Xilinx library for simulation",
    "digital-ide.function.simulate.runInTerminal.title": "Run the simulation command in the terminal instead of the output",
    "digital-ide.function.lsp.formatter.vlog.default.style.title": "Select the Verilog and SystemVerilog formatter style.",
    "digital-ide.function.lsp.formatter.vlog.default.args.title": "Add Verilog formatter arguments here (like istyle).",
    "digital-ide.function.lsp.formatter.vhdl.default.keyword-case.title": "Keyword case",
    "digital-ide.function.lsp.formatter.vhdl.default.align-comments.title": "Align comments",
    "digital-ide.function.lsp.formatter.vhdl.default.type-name-case.title": "Type name case",
    "digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "Indentation",
    "digital-ide.function.lsp.completion.vlog.auto-add-include.title": "When triggering module auto-completion, if the top include macro does not include the file where the instantiated module is located, automatically add `include \"xxx.v\" at the top of the file",
    "digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "When triggering module auto-completion, automatically generate the declaration of output type signals above the instantiated module",
    "digital-ide.function.lsp.linter.verilog.diagnostor.title": "Choose the diagnostor to do linter in editing Verilog",
    "digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
    "digital-ide.function.lsp.linter.vhdl.diagnostor.title": "Choose the diagnostor to do linter in editing VHDL",
    "digital-ide.function.instantiation.addComment.title": "Add comments like // ports, // input, // output when doing instantiation, including completion for module invoking",
    "digital-ide.function.instantiation.autoNetOutputDeclaration.title": "Automatically declare output type nets in the scope when instantiation happens.",
    "fpga-support.onTypeFormattingTriggerCharacters.title": "Trigger characters for onTypeFormatting",
    "digital-ide.function.lsp.file-parse-maxsize.title": "",
    "digital-ide.structure.from-xilinx-to-standard.title": "Convert Xilinx projects to Digital IDE standard project structure",
    "digital-ide.prj.verible.install.path.title": "Installation directory path for verible, which is the absolute path of the folder containing the verible-verilog-syntax executable. If not specified, verible-verilog-syntax will be used for diagnostics by default.",
    "digital-ide.prj.verilator.install.path.title": "Installation directory path for verilator, which is the absolute path of the folder containing the verilator executable. If not specified, verilator will be used for diagnostics by default.",
    "digital-ide.function.lsp.linter.mode.title": "Specify the diagnostic mode of the linter",
    "digital-ide.function.lsp.linter.mode.0.title": "Diagnose all design sources directly and report errors, regardless of whether the files are open.",
    "digital-ide.function.lsp.linter.mode.1.title": "When a single file is closed, the corresponding error is removed, and only the file that is opened is diagnosed.",
    "digital-ide.function.lsp.linter.mode.2.title": "Globally disabled, meaning no project errors are reported for the entire project.",
    "digital-ide.function.lsp.linter.linter-level.title": "Diagnostic Level Settings for the Linter",
    "digital-ide.function.lsp.linter.linter-level.error.title": "Show Only Errors",
    "digital-ide.function.lsp.linter.linter-level.warning.title": "Show Errors and Warnings",
    "digital-ide.function.netlist.schema-mode.title": "Select Netlist Synthesis Mode",
    "digital-ide.function.netlist.schema-mode.0.title": "Pre-Behavioral Synthesis",
    "digital-ide.function.netlist.schema-mode.1.title": "Post-Behavioral Synthesis",
    "digital-ide.function.netlist.schema-mode.2.title": "Post-RTL Synthesis",
    "digital-ide.run-ys.title": "Run yosys script",
    "digital-ide.function.lsp.crashForensics.enabled.title": "Automatically capture Digital Server crash evidence on Windows",
    "digital-ide.function.lsp.crashForensics.fullMemoryDump.title": "Include full process memory in Digital Server crash dumps",
    "digital-ide.function.lsp.crashForensics.retainedSessions.title": "Maximum number of Digital Server crash evidence sessions to retain",
    "digital-ide.server.openCrashEvidence.title": "Open Latest Server Crash Evidence",
    "digital-ide.server.exportCrashEvidence.title": "Export Latest Server Crash Evidence"
}