Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.

Interfacing VHDL and foreign languages with VUnit

Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.

GTKWave Decoders for RISCV

Set of utilities to export/import FMUs out of existing C++ code

ModelScript is a completely web-native, polyglot incremental compiler supporting multiple engineering domains — from requirements and system architecture to simulation, CAD, CAE, and manufacturing. By natively supporting Modelica, SysML v2, and STEP, ModelScript enables seamless cross-domain simulation-based requirements verification.

Cosimulator for the Violet core: https://github.com/losfair/Violet

Enables the co-simulation between PSS/E and Matlab/Simulink

Repositório de organização geral do projeto openTES

Python AES

CoSys MAP 2020: Integrating Physical and Virtual Objects in a Simulation Environment

AES-128 co-simulation between SystemVerilog, C DPI, and Python for hardware verification.

coherence integrates evolutionary computation and co-simulation for the systematic design of protocols for cell culture and biofabrication.

Aspycot: A Spike and Python CO-Simulation Testbench for hardware monitoring IPs