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clock-domain-crossing
Here are 14 public repositories matching this topic...
Asynchronous FIFO for transferring data between two asynchronous clock domains
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Jun 3, 2016 - Verilog
FIFO implementation with different clock domains for read and write.
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Aug 17, 2021 - Verilog
In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.
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Nov 20, 2020 - VHDL
Final project for the class "Application Specific Integrated Circuit Development"
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Oct 21, 2021 - SystemVerilog
Utilities for clock-domain crossing with an FPGA
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Jun 27, 2020 - SystemVerilog
A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs
fpga communication-protocol asynchronous embedded-systems fault-tolerant fault-detection network-on-chip interchip-bridge clock-domain-crossing
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Oct 30, 2017 - VHDL
Dual-clock asynchronous FIFO in Verilog using Gray-coded CDC pointers, dual-port memory, full/empty flag logic, and a self-checking verification testbench.
fpga eda rtl verilog hardware-designs fifo cdc vlsi digital-design digital-systems asy clock-domain-crossing
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Feb 1, 2026 - Verilog
Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog
asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design
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Nov 20, 2025 - SystemVerilog
RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.
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May 18, 2025 - Verilog
Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and parameterized design. Essential for SoC inter-module communication and multi-clock systems.
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Dec 5, 2025 - Verilog
Hardware button debouncer with metastability protection - VHDL synchronizer chains and CDC fundamentals for reliable input handling
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Jan 24, 2026 - Tcl
A basic SPI Slave implementation for Artix-7 FPGA (Basys 3) driven by an ESP32. Features a custom ALU with MAC support and proper CDC synchronization
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Mar 5, 2026 - SystemVerilog
Hardware button debouncer with metastability protection - VHDL synchronizer chains and CDC fundamentals for reliable input handling
fpga vhdl xilinx synchronizer cdc debouncing metastability clock-domain-crossing artix-7 hardware-design
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Jan 24, 2026 - Tcl
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