Memory Management Unit (MMU) Design using Verilog HDL

Overview

This project implements a simplified Memory Management Unit (MMU) using Verilog HDL. The design performs virtual-to-physical address translation, memory protection, page validation, and permission checking. The project demonstrates fundamental concepts used in modern processors and operating systems.

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Features

• Virtual Address Translation
• Physical Address Generation
• Page Table Lookup
• Valid Bit Verification
• Read Permission Checking
• Write Permission Checking
• Page Fault Detection
• Protection Fault Detection
• Verilog RTL Implementation
• Self-Checking Testbench
• GTKWave Verification

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Architecture

Virtual Address ↓ Page Number Extraction ↓ Page Table Lookup ↓ Valid Bit Check ↓ Permission Check ↓ Frame Mapping ↓ Physical Address Output

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Design Specifications

Parameter	Value
Virtual Address Width	16 bits
Physical Address Width	16 bits
Page Size	256 Bytes
VPN Width	8 bits
Offset Width	8 bits

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Project Structure

MMU-Design-Verilog-HDL/

├── rtl/ ├── tb/ ├── reports/ ├── simulation/ ├── waveforms/ ├── README.md └── .gitignore

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Tools Used

• Verilog HDL
• Visual Studio Code
• Icarus Verilog
• GTKWave

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Simulation Commands

iverilog -o mmu_sim rtl/mmu.v tb/mmu_tb.v

vvp mmu_sim

gtkwave waveforms/mmu.vcd

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Test Cases

Test Case	Result
Valid Translation	PASS
Invalid Page	PASS
Write Protection Fault	PASS
Valid Read Access	PASS

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Waveform Verification

The generated waveform verifies:

• Successful address translation
• Page fault generation
• Protection fault generation
• Translation validity

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Applications

• Processor Design
• Virtual Memory Systems
• Operating Systems
• Embedded Systems
• Secure Computing
• Computer Architecture Education

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Future Enhancements

• Translation Lookaside Buffer (TLB)
• ASID Support
• LRU Replacement
• Multi-level Page Tables
• Page Table Walker
• AXI Interface

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