feat(riscv): add sireg CSR

riscv/CHANGELOG.md

@@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
-- Add `mireg` CSR
+- Add `mireg` and `sireg` CSRs
 - Add `stopei` and `vstopei` CSRs (AIA supervisor/virtual-supervisor top external
   interrupt), completing the `*topei` set alongside `mtopei`.
 - Auto-generate `<FIELD>_SHIFT`, `<FIELD>_WIDTH`, and `<FIELD>_MASK` associated

riscv/src/register.rs

@@ -131,6 +131,7 @@ pub mod mseccfgh;
 pub mod miselect;
 
 // Supervisor indirect access
+pub mod sireg;
 pub mod siselect;
 
 // Virtual supervisor indirect access

riscv/src/register/sireg.rs

@@ -0,0 +1,14 @@
+//! 'sireg' register (Supervisor Indirect Register Alias)
+//!
+//! CSR address: 0x151
+//!
+//! The `sireg` register provides access to an indirect register
+//! selected by `siselect`.
+
+const MASK: usize = usize::MAX;
+
+read_write_csr! {
+    /// `sireg` register.
+    Sireg: 0x151,
+    mask: MASK
+}