Added RVA23 coverage and test generators

README.md

@@ -249,6 +249,10 @@ The ACT Framework uses a selection of assembly macros to run DUT-specific code t
 - `RVMODEL_MTIMECMP_ADDRESS` (can be omitted if MTIMECMP is not implemented)
 - `RVMODEL_TIMER_INT_SOON_DELAY`
 
+**MSIP Macro**: Required only for Sm version 1.13 and above. Can be omitted if machine software interrupts are not supported.
+
+- `RVMODEL_MSIP_ADDRESS` (can be omitted if MSIP is not memory-mapped or not tested)
+
 **Interrupt Macros**: Can be left blank if interrupts are not supported.
 
 - `RVMODEL_SET_MEXT_INT(_R1, _R2)`

config/cores/cvw/ci.yaml

@@ -3,8 +3,9 @@
 # CI configuration for CORE-V Wally (CVW)
 # Requires Verilator and the CVW repository
 
+# TODO: remove za64rs from excluded_extensions when Sail supports UDB_LRSC_FAIL_ON_NON_EXACT_LRSC to match DUT
 ci_enabled: true
-exclude_extensions: "Sm,S,InterruptsU,PMPSm,ExceptionsZalrsc,ExceptionsZaamo"
+exclude_extensions: "Sm,S,InterruptsU,PMPSm,ExceptionsZalrsc,ExceptionsZaamo,Za64rs"
 apt_packages: "autoconf flex bison help2man libfl-dev ccache"
 install_script: ".github/scripts/install-cvw.sh"
 setup_script: ".github/scripts/setup-cvw.sh"

config/cores/cvw/cvw-rv64gc/rvmodel_macros.h

@@ -98,19 +98,19 @@
 ##### Machine Interrupts #####
 
 #define CLINT_BASE_ADDRESS 0x02000000
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 #define RVMODEL_SET_MEXT_INT(_R1, _R2)
 
 #define RVMODEL_CLR_MEXT_INT(_R1, _R2)
 
 #define RVMODEL_SET_MSW_INT(_R1, _R2) \
   li _R1, 1; \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw _R1, 0(_R2);
 
 #define RVMODEL_CLR_MSW_INT(_R1, _R2) \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw zero, 0(_R2);
 
 ##### Supervisor Interrupts #####

config/imperas/imperas-rv64-max/rvmodel_macros.h

@@ -100,16 +100,16 @@
   sw zero, 0(_R2)            ; /* Clear MEXT interrupt */ \
 
 
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 #define RVMODEL_SET_MSW_INT(_R1, _R2)        \
   li _R1, 1;                 \
-  li _R2, MSIP_ADDRESS;              \
+  li _R2, RVMODEL_MSIP_ADDRESS;              \
   sw _R1, 0(_R2);
 
 
 #define RVMODEL_CLR_MSW_INT(_R1, _R2)        \
-  li _R2, MSIP_ADDRESS;              \
+  li _R2, RVMODEL_MSIP_ADDRESS;              \
   sw zero, 0(_R2);
 
 

config/qemu/ci.yaml

@@ -5,6 +5,7 @@
 
 ci_enabled: true
 # TODO: Priv tests mismatch due to config issues. Atomics failure still needs to be diagnosed.
-exclude_extensions: "Sm,S,Zalrsc,Zacas,ZacasZabha,InterruptsSm,PMPSm,PMPmisaligned,ExceptionsZalrsc,ExceptionsZicboU,ExceptionsZicboS,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo"
+# TODO: remove za64rs from excluded_extensions when Sail supports UDB_LRSC_FAIL_ON_NON_EXACT_LRSC to match DUT
+exclude_extensions: "Sm,S,Zalrsc,Zacas,ZacasZabha,InterruptsSm,PMPSm,PMPmisaligned,ExceptionsZalrsc,ExceptionsZicboU,ExceptionsZicboS,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo,Za64rs"
 install_script: ".github/scripts/install-qemu.sh"
 apt_packages: "libglib2.0-dev libfdt-dev libpixman-1-dev zlib1g-dev ninja-build"

config/qemu/qemu-rv64-max/rvmodel_macros.h

@@ -164,19 +164,19 @@
 #define RVMODEL_TIMER_INT_SOON_DELAY 100
 
 #define CLINT_BASE_ADDRESS 0x02000000
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 #define RVMODEL_SET_MEXT_INT(_R1, _R2)
 
 #define RVMODEL_CLR_MEXT_INT(_R1, _R2)
 
 #define RVMODEL_SET_MSW_INT(_R1, _R2) \
   li _R1, 1; \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw _R1, 0(_R2);
 
 #define RVMODEL_CLR_MSW_INT(_R1, _R2) \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw zero, 0(_R2);
 
 ##### Supervisor Interrupts #####

config/sail/sail-rv64-max/rvmodel_macros.h

@@ -102,16 +102,16 @@
   sw zero, 0(_R2)            ; /* Clear MEXT interrupt */ \
 
 
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 #define RVMODEL_SET_MSW_INT(_R1, _R2)        \
   li _R1, 1;                 \
-  li _R2, MSIP_ADDRESS;              \
+  li _R2, RVMODEL_MSIP_ADDRESS;              \
   sw _R1, 0(_R2);
 
 
 #define RVMODEL_CLR_MSW_INT(_R1, _R2)        \
-  li _R2, MSIP_ADDRESS;              \
+  li _R2, RVMODEL_MSIP_ADDRESS;              \
   sw zero, 0(_R2);
 
 

config/spike/ci.yaml

@@ -5,6 +5,7 @@
 
 ci_enabled: true
 # TODO: Priv tests mismatch due to config issues. Atomics failure still needs to be diagnosed.
-exclude_extensions: "Sm,ExceptionsZc,S,InterruptsSm,PMPmisaligned,ExceptionsZalrsc,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo"
+# TODO: remove za64rs from excluded_extensions when Sail supports UDB_LRSC_FAIL_ON_NON_EXACT_LRSC to match DUT
+exclude_extensions: "Sm,ExceptionsZc,S,InterruptsSm,PMPmisaligned,ExceptionsZalrsc,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo,Za64rs"
 install_script: ".github/scripts/install-spike.sh"
 apt_packages: "device-tree-compiler libboost-regex-dev libboost-system-dev"

config/spike/spike-rv64-max/rvmodel_macros.h

@@ -99,19 +99,19 @@
 #define RVMODEL_TIMER_INT_SOON_DELAY 100
 
 #define CLINT_BASE_ADDRESS 0x02000000
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 #define RVMODEL_SET_MEXT_INT(_R1, _R2)
 
 #define RVMODEL_CLR_MEXT_INT(_R1, _R2)
 
 #define RVMODEL_SET_MSW_INT(_R1, _R2) \
   li _R1, 1; \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw _R1, 0(_R2);
 
 #define RVMODEL_CLR_MSW_INT(_R1, _R2) \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw zero, 0(_R2);
 
 ##### Supervisor Interrupts #####

config/whisper/whisper-rv32-max/rvtest_config.h

@@ -12,7 +12,7 @@
 #define LARGEST_PROGRAM     0x00010000
 
 #define CLINT_BASE_ADDRESS 0x02000000
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 
 #define A_SUPPORTED

config/whisper/whisper-rv64-max/rvmodel_macros.h

@@ -84,11 +84,11 @@
 
 #define RVMODEL_SET_MSW_INT(_R1, _R2) \
   li _R1, 1; \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw _R1, 0(_R2);
 
 #define RVMODEL_CLR_MSW_INT(_R1, _R2) \
-  li _R2, MSIP_ADDRESS; \
+  li _R2, RVMODEL_MSIP_ADDRESS; \
   sw zero, 0(_R2);
 
 ##### Supervisor Interrupts #####

config/whisper/whisper-rv64-max/rvtest_config.h

@@ -14,7 +14,7 @@
 #define LARGEST_PROGRAM     0x00010000
 
 #define CLINT_BASE_ADDRESS 0x02000000
-#define MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
+#define  RVMODEL_MSIP_ADDRESS (CLINT_BASE_ADDRESS + 0x0)
 
 
 #define A_SUPPORTED

coverpoints/coverage/RISCV_coverage_base_init.svh

@@ -214,6 +214,10 @@
         `cover_info("//      SsstrictV - Enabled");
         `include "SsstrictV_coverage_init.svh"
     `endif
+    `ifdef COVER_SSU64XL
+        `cover_info("//      Ssu64xl - Enabled");
+        `include "Ssu64xl_coverage_init.svh"
+    `endif
     `ifdef COVER_SV
         `cover_info("//      Sv - Enabled");
         `include "Sv_coverage_init.svh"
@@ -326,6 +330,10 @@
         `cover_info("//      Vx8 - Enabled");
         `include "Vx8_coverage_init.svh"
     `endif
+    `ifdef COVER_ZA64RS
+        `cover_info("//      Za64rs - Enabled");
+        `include "Za64rs_coverage_init.svh"
+    `endif
     `ifdef COVER_ZAAMO
         `cover_info("//      Zaamo - Enabled");
         `include "Zaamo_coverage_init.svh"
@@ -446,6 +454,10 @@
         `cover_info("//      ZfhminD - Enabled");
         `include "ZfhminD_coverage_init.svh"
     `endif
+    `ifdef COVER_ZIC64BZICBOZ
+        `cover_info("//      Zic64bzicboz - Enabled");
+        `include "Zic64bzicboz_coverage_init.svh"
+    `endif
     `ifdef COVER_ZICBOM
         `cover_info("//      Zicbom - Enabled");
         `include "Zicbom_coverage_init.svh"

coverpoints/coverage/RISCV_coverage_base_sample.svh

@@ -163,6 +163,9 @@
     `ifdef COVER_SSSTRICTV
         ssstrictv_sample(hart, issue, ins);
     `endif
+    `ifdef COVER_SSU64XL
+        ssu64xl_sample(hart, issue, ins);
+    `endif
     `ifdef COVER_SV
         sv_sample(hart, issue, ins);
     `endif
@@ -247,6 +250,9 @@
     `ifdef COVER_VX8
         vx8_sample(hart, issue, ins);
     `endif
+    `ifdef COVER_ZA64RS
+        za64rs_sample(hart, issue, ins);
+    `endif
     `ifdef COVER_ZAAMO
         zaamo_sample(hart, issue, ins);
     `endif
@@ -337,6 +343,9 @@
     `ifdef COVER_ZFHMIND
         zfhmind_sample(hart, issue, ins);
     `endif
+    `ifdef COVER_ZIC64BZICBOZ
+        zic64bzicboz_sample(hart, issue, ins);
+    `endif
     `ifdef COVER_ZICBOM
         zicbom_sample(hart, issue, ins);
     `endif

coverpoints/coverage/RISCV_coverage_config.svh

@@ -164,6 +164,9 @@
 `ifdef SSSTRICTV_COVERAGE
   `include "SsstrictV_coverage.svh"
 `endif
+`ifdef SSU64XL_COVERAGE
+  `include "Ssu64xl_coverage.svh"
+`endif
 `ifdef SV_COVERAGE
   `include "Sv_coverage.svh"
 `endif
@@ -248,6 +251,9 @@
 `ifdef VX8_COVERAGE
   `include "Vx8_coverage.svh"
 `endif
+`ifdef ZA64RS_COVERAGE
+  `include "Za64rs_coverage.svh"
+`endif
 `ifdef ZAAMO_COVERAGE
   `include "Zaamo_coverage.svh"
 `endif
@@ -338,6 +344,9 @@
 `ifdef ZFHMIND_COVERAGE
   `include "ZfhminD_coverage.svh"
 `endif
+`ifdef ZIC64BZICBOZ_COVERAGE
+  `include "Zic64bzicboz_coverage.svh"
+`endif
 `ifdef ZICBOM_COVERAGE
   `include "Zicbom_coverage.svh"
 `endif

coverpoints/priv/S_coverage.svh

@@ -80,6 +80,7 @@ covergroup S_scause_cg with function sample(ins_t ins);
     // main coverpoints
     cp_scause_write_exception: cross priv_mode_s, csrrw, scause, scause_exception_values, scause_exception; // CSR write of scause in S mode with interesting values
     cp_scause_write_interrupt: cross priv_mode_s, csrrw, scause, scause_interrupt_values, scause_interrupt; // CSR write of scause in S mode with interesting values
+
 endgroup
 
 
@@ -104,6 +105,20 @@ covergroup S_sstatus_cg with function sample(ins_t ins);
     // main coverpoints
     cp_sstatus_sd_write: cross priv_mode_s, csrrw, sstatus, cp_sstatus_sd, cp_sstatus_fs, cp_sstatus_vs, cp_sstatus_xs;
 
+    `ifdef SS1P13_SUPPORTED
+        `ifdef XLEN64
+            uxl_write_attempt: coverpoint ins.current.rs1_val[33:32] {
+                bins attempt_1 = {2'b01};
+                bins attempt_2 = {2'b10};
+            }
+            csrop: coverpoint ins.current.insn {
+                wildcard bins csrrw = {CSRRW};
+            }
+             // main coverpoints
+            cp_sxlen_ge_uxlen: cross priv_mode_s, csrop, sstatus, uxl_write_attempt;
+        `endif // XLEN64
+    `endif // SS1P13_SUPPORTED
+
 endgroup
 
 covergroup S_sprivinst_cg with function sample(ins_t ins);

coverpoints/priv/Sm_coverage.svh

@@ -79,6 +79,7 @@ covergroup Sm_mcause_cg with function sample(ins_t ins);
     // This is Sm machine-mode testing, so all coverpoints are in Machine mode.
     cp_mcause_write_exception: cross priv_mode_m, csrrw, mcause, mcause_exception_values, mcause_exception; // CSR write of mcause in M mode with interesting values
     cp_mcause_write_interrupt: cross priv_mode_m, csrrw, mcause, mcause_interrupt_values, mcause_interrupt; // CSR write of mcause in M mode with interesting values
+
 endgroup
 
 
@@ -413,6 +414,42 @@ covergroup Sm_mcsr_cg with function sample(ins_t ins);
             cp_mtimeh_write :   cross priv_mode_m, csrr,  timeh_csr; // assumes mtimeh has been written
         `endif
     `endif
+
+    `ifdef SM1P13_SUPPORTED
+        misa_b_bit: coverpoint ins.current.rs1_val[1] {
+            bins b_set   = {1'b1};
+            bins b_clear = {1'b0};
+        }
+        misa_v_bit: coverpoint ins.current.rs1_val[21] {
+            bins v_set   = {1'b1};
+            bins v_clear = {1'b0};
+        }
+
+        cp_misa_b: cross priv_mode_m, misa, csrop, misa_b_bit;
+        cp_misa_v: cross priv_mode_m, misa, csrop, misa_v_bit;
+
+
+        `ifdef RVMODEL_MSIP_ADDRESS
+            msip_address: coverpoint ins.current.rs1_val {
+                bin msip = {`RVMODEL_MSIP_ADDRESS};
+            }
+            msip_val: coverpoint ins.current.rs2_val {
+                bin zero = {0};
+                bin one  = {1};
+            }
+            cp_msip: cross priv_mode_m, sw, msip_address, msip_val;
+        `endif // RVMODEL_MSIP_ADDRESS
+
+        `ifdef XLEN32
+            medelegh: coverpoint ins.current.insn[31:20] {
+                bins medelegh = {CSR_MEDELEGH};
+            }
+
+            cp_medelegh: cross priv_mode_m, csrrw, medelegh, rs1_ones; // RV32 only: write all 1s to medelegh and read back
+        `endif // XLEN32
+    `endif // SM1P13_SUPPORTED
+
+
 endgroup
 
 function void sm_sample(int hart, int issue, ins_t ins);

coverpoints/priv/Ssu64xl_coverage.svh

@@ -0,0 +1,37 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups
+//
+// Written: Ammarah Wakeel  email:ammarahwakeel9@gmail.com (UET, April 2026)
+//
+// Copyright (C) : 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: Coverage for RVA23 profile - Ssu64xl extension
+//
+///////////////////////////////////////////////
+
+`define COVER_SSU64XL
+
+covergroup Ssu64xl_cg with function sample(ins_t ins);
+    option.per_instance = 0;
+
+    `include "general/RISCV_coverage_standard_coverpoints.svh"
+
+    `ifdef XLEN64
+
+        sstatus_uxl_after: coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_AFTER, "sstatus", "uxl") {
+            bins uxl_is_10 = {2'b10};
+        }
+        gpr_bit63: coverpoint ins.current.rd_val[63] {
+            bins bit63_set = {1'b1};
+        }
+
+        cp_ssu64xl: cross priv_mode_u, sstatus_uxl_after, gpr_bit63;
+
+    `endif
+
+endgroup
+
+function void ssu64xl_sample(int hart, int issue, ins_t ins);
+    Ssu64xl_cg.sample(ins);
+endfunction