Added RVA23 coverage and test generators

config/cores/cvw/ci.yaml

@@ -4,7 +4,7 @@
 # Requires Verilator and the CVW repository
 
 ci_enabled: true
-exclude_extensions: "Sm,S,InterruptsU,PMPSm,ExceptionsZalrsc,ExceptionsZaamo"
+exclude_extensions: "Sm,S,InterruptsU,PMPSm,ExceptionsZalrsc,ExceptionsZaamo,Za64rs"
 apt_packages: "autoconf flex bison help2man libfl-dev ccache"
 install_script: ".github/scripts/install-cvw.sh"
 setup_script: ".github/scripts/setup-cvw.sh"

config/qemu/ci.yaml

@@ -5,6 +5,6 @@
 
 ci_enabled: true
 # TODO: Priv tests mismatch due to config issues. Atomics failure still needs to be diagnosed.
-exclude_extensions: "Sm,S,Zalrsc,Zacas,ZacasZabha,InterruptsSm,PMPSm,PMPmisaligned,ExceptionsZalrsc,ExceptionsZicboU,ExceptionsZicboS,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo"
+exclude_extensions: "Sm,S,Zalrsc,Zacas,ZacasZabha,InterruptsSm,PMPSm,PMPmisaligned,ExceptionsZalrsc,ExceptionsZicboU,ExceptionsZicboS,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo,Za64rs"
 install_script: ".github/scripts/install-qemu.sh"
 apt_packages: "libglib2.0-dev libfdt-dev libpixman-1-dev zlib1g-dev ninja-build"

config/spike/ci.yaml

@@ -5,6 +5,6 @@
 
 ci_enabled: true
 # TODO: Priv tests mismatch due to config issues. Atomics failure still needs to be diagnosed.
-exclude_extensions: "Sm,ExceptionsZc,S,InterruptsSm,PMPmisaligned,ExceptionsZalrsc,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo"
+exclude_extensions: "Sm,ExceptionsZc,S,InterruptsSm,PMPmisaligned,ExceptionsZalrsc,Svadu,SvaduPMP,Svnapot,Svpbmt,SvZicbo,ExceptionsZaamo,Za64rs"
 install_script: ".github/scripts/install-spike.sh"
 apt_packages: "device-tree-compiler libboost-regex-dev libboost-system-dev"

coverpoints/coverage/RISCV_coverage_base_init.svh

@@ -214,6 +214,10 @@
         `cover_info("//      SsstrictV - Enabled");
         `include "SsstrictV_coverage_init.svh"
     `endif
+    `ifdef COVER_SSU64XL
+        `cover_info("//      Ssu64xl - Enabled");
+        `include "Ssu64xl_coverage_init.svh"
+    `endif
     `ifdef COVER_SV
         `cover_info("//      Sv - Enabled");
         `include "Sv_coverage_init.svh"
@@ -326,6 +330,10 @@
         `cover_info("//      Vx8 - Enabled");
         `include "Vx8_coverage_init.svh"
     `endif
+    `ifdef COVER_ZA64RS
+        `cover_info("//      Za64rs - Enabled");
+        `include "Za64rs_coverage_init.svh"
+    `endif
     `ifdef COVER_ZAAMO
         `cover_info("//      Zaamo - Enabled");
         `include "Zaamo_coverage_init.svh"
@@ -446,6 +454,10 @@
         `cover_info("//      ZfhminD - Enabled");
         `include "ZfhminD_coverage_init.svh"
     `endif
+    `ifdef COVER_ZIC64BZICBOZ
+        `cover_info("//      Zic64bzicboz - Enabled");
+        `include "Zic64bzicboz_coverage_init.svh"
+    `endif
     `ifdef COVER_ZICBOM
         `cover_info("//      Zicbom - Enabled");
         `include "Zicbom_coverage_init.svh"

coverpoints/coverage/RISCV_coverage_base_sample.svh

@@ -163,6 +163,9 @@
     `ifdef COVER_SSSTRICTV
         ssstrictv_sample(hart, issue, ins);
     `endif
+    `ifdef COVER_SSU64XL
+        ssu64xl_sample(hart, issue, ins);
+    `endif
     `ifdef COVER_SV
         sv_sample(hart, issue, ins);
     `endif
@@ -247,6 +250,9 @@
     `ifdef COVER_VX8
         vx8_sample(hart, issue, ins);
     `endif
+    `ifdef COVER_ZA64RS
+        za64rs_sample(hart, issue, ins);
+    `endif
     `ifdef COVER_ZAAMO
         zaamo_sample(hart, issue, ins);
     `endif
@@ -337,6 +343,9 @@
     `ifdef COVER_ZFHMIND
         zfhmind_sample(hart, issue, ins);
     `endif
+    `ifdef COVER_ZIC64BZICBOZ
+        zic64bzicboz_sample(hart, issue, ins);
+    `endif
     `ifdef COVER_ZICBOM
         zicbom_sample(hart, issue, ins);
     `endif

coverpoints/coverage/RISCV_coverage_config.svh

@@ -164,6 +164,9 @@
 `ifdef SSSTRICTV_COVERAGE
   `include "SsstrictV_coverage.svh"
 `endif
+`ifdef SSU64XL_COVERAGE
+  `include "Ssu64xl_coverage.svh"
+`endif
 `ifdef SV_COVERAGE
   `include "Sv_coverage.svh"
 `endif
@@ -248,6 +251,9 @@
 `ifdef VX8_COVERAGE
   `include "Vx8_coverage.svh"
 `endif
+`ifdef ZA64RS_COVERAGE
+  `include "Za64rs_coverage.svh"
+`endif
 `ifdef ZAAMO_COVERAGE
   `include "Zaamo_coverage.svh"
 `endif
@@ -338,6 +344,9 @@
 `ifdef ZFHMIND_COVERAGE
   `include "ZfhminD_coverage.svh"
 `endif
+`ifdef ZIC64BZICBOZ_COVERAGE
+  `include "Zic64bzicboz_coverage.svh"
+`endif
 `ifdef ZICBOM_COVERAGE
   `include "Zicbom_coverage.svh"
 `endif

coverpoints/priv/S_coverage.svh

@@ -80,6 +80,7 @@ covergroup S_scause_cg with function sample(ins_t ins);
     // main coverpoints
     cp_scause_write_exception: cross priv_mode_s, csrrw, scause, scause_exception_values, scause_exception; // CSR write of scause in S mode with interesting values
     cp_scause_write_interrupt: cross priv_mode_s, csrrw, scause, scause_interrupt_values, scause_interrupt; // CSR write of scause in S mode with interesting values
+
 endgroup
 
 
@@ -104,6 +105,23 @@ covergroup S_sstatus_cg with function sample(ins_t ins);
     // main coverpoints
     cp_sstatus_sd_write: cross priv_mode_s, csrrw, sstatus, cp_sstatus_sd, cp_sstatus_fs, cp_sstatus_vs, cp_sstatus_xs;
 
+    `ifdef SS1P13_SUPPORTED
+        `ifdef XLEN64
+            uxl_write_attempt: coverpoint ins.current.rs1_val[33:32] {
+                bins attempt_1 = {2'b01};
+                bins attempt_2 = {2'b10};
+            }
+            sstatus_uxl_after: coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_AFTER, "sstatus", "uxl") {
+                // empty bins: auto-observes what DUT actually stored, no assertion on value
+            }
+            csrop: coverpoint ins.current.insn {
+                wildcard bins csrrw = {CSRRW};
+            }
+             // main coverpoints
+            cp_sxlen_ge_uxlen: cross priv_mode_s, csrop, sstatus, uxl_write_attempt, sstatus_uxl_after;
+        `endif // XLEN64
+    `endif // SS1P13_SUPPORTED
+
 endgroup
 
 covergroup S_sprivinst_cg with function sample(ins_t ins);

coverpoints/priv/Sm_coverage.svh

@@ -79,6 +79,7 @@ covergroup Sm_mcause_cg with function sample(ins_t ins);
     // This is Sm machine-mode testing, so all coverpoints are in Machine mode.
     cp_mcause_write_exception: cross priv_mode_m, csrrw, mcause, mcause_exception_values, mcause_exception; // CSR write of mcause in M mode with interesting values
     cp_mcause_write_interrupt: cross priv_mode_m, csrrw, mcause, mcause_interrupt_values, mcause_interrupt; // CSR write of mcause in M mode with interesting values
+
 endgroup
 
 
@@ -413,6 +414,38 @@ covergroup Sm_mcsr_cg with function sample(ins_t ins);
             cp_mtimeh_write :   cross priv_mode_m, csrr,  timeh_csr; // assumes mtimeh has been written
         `endif
     `endif
+
+    `ifdef SM1P13_SUPPORTED
+        misa_b_bit: coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_AFTER, "misa", "b")[0] {
+            bins b_set   = {1'b1};
+            bins b_clear = {1'b0};
+        }
+        misa_v_bit: coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_AFTER, "misa", "v")[0] {
+            bins v_set   = {1'b1};
+            bins v_clear = {1'b0};
+        }
+        mip_csr: coverpoint ins.current.insn[31:20] {
+            bins mip = {CSR_MIP};
+        }
+        mip_msip_after: coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_AFTER, "mip", "msip")[0] {
+            bins msip_set   = {1'b1};
+            bins msip_clear = {1'b0};
+        }
+
+        cp_misa_b: cross priv_mode_m, misa, csrop, misa_b_bit;
+        cp_misa_v: cross priv_mode_m, misa, csrop, misa_v_bit;
+        cp_msip: cross priv_mode_m, csrr, mip_csr, mip_msip_after;
+
+        `ifdef XLEN32
+            medelegh: coverpoint ins.current.insn[31:20] {
+                bins medelegh = {CSR_MEDELEGH};
+            }
+
+            cp_medelegh: cross priv_mode_m, csrrw, medelegh, rs1_ones; // RV32 only: write all 1s to medelegh and read back
+        `endif // XLEN32
+    `endif // SM1P13_SUPPORTED
+
+
 endgroup
 
 function void sm_sample(int hart, int issue, ins_t ins);

coverpoints/priv/Ssu64xl_coverage.svh

@@ -0,0 +1,37 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups
+//
+// Written: Ammarah Wakeel  email:ammarahwakeel9@gmail.com (UET, April 2026)
+//
+// Copyright (C) : 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: Coverage for RVA23 profile - Ssu64xl extension
+//
+///////////////////////////////////////////////
+
+`define COVER_SSU64XL
+
+covergroup Ssu64xl_cg with function sample(ins_t ins);
+    option.per_instance = 0;
+
+    `include "general/RISCV_coverage_standard_coverpoints.svh"
+
+    `ifdef XLEN64
+
+        sstatus_uxl_after: coverpoint get_csr_val(ins.hart, ins.issue, `SAMPLE_AFTER, "sstatus", "uxl") {
+            bins uxl_is_10 = {2'b10};
+        }
+        gpr_bit63: coverpoint ins.current.rd_val[63] {
+            bins bit63_set = {1'b1};
+        }
+
+        cp_ssu64xl: cross priv_mode_u, sstatus_uxl_after, gpr_bit63;
+
+    `endif
+
+endgroup
+
+function void ssu64xl_sample(int hart, int issue, ins_t ins);
+    Ssu64xl_cg.sample(ins);
+endfunction

coverpoints/priv/Ssu64xl_coverage_init.svh

@@ -0,0 +1,11 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups Initialization File
+//
+// Copyright (C) 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+///////////////////////////////////////////////
+
+Ssu64xl_cg = new();
+Ssu64xl_cg.set_inst_name("obj_Ssu64xl");

coverpoints/priv/Za64rs_coverage.svh

@@ -0,0 +1,38 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups
+//
+// Written:  Ammarah Wakeel  email:ammarahwakeel9@gmail.com (UET, April 2026)
+//
+// Copyright (C) : 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: Coverage for Za64rs extension (Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes)
+///////////////////////////////////////////////
+
+
+`define COVER_ZA64RS
+
+covergroup Za64rs_cg with function sample(ins_t ins);
+    option.per_instance = 0;
+    `include "general/RISCV_coverage_standard_coverpoints.svh"
+
+    lr_w_instr: coverpoint ins.prev.insn {
+        wildcard bins lr_w = {LR_W};
+    }
+    sc_w_instr: coverpoint ins.current.insn {
+        wildcard bins sc_w = {SC_W};
+    }
+    lr_w_base_aligned: coverpoint ins.prev.rs1_val[5:0] {
+        bins aligned_64 = {6'd0};
+    }
+    sc_offset: coverpoint ins.current.rs1_val[6:0] {
+         bins offset_aligned[] = {[7'd0 : 7'd64]} with (item % 4 == 0);
+    }
+
+    cp_za64rs: cross  sc_w_instr, sc_offset, lr_w_instr, lr_w_base_aligned ;
+
+endgroup
+
+function void za64rs_sample(int hart, int issue, ins_t ins);
+    Za64rs_cg.sample(ins);
+endfunction

coverpoints/priv/Za64rs_coverage_init.svh

@@ -0,0 +1,11 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups Initialization File
+//
+// Copyright (C) 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+///////////////////////////////////////////////
+
+Za64rs_cg = new();
+Za64rs_cg.set_inst_name("obj_Za64rs");

coverpoints/priv/Zic64bzicboz_coverage.svh

@@ -0,0 +1,31 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups
+//
+// Written:  Ammarah Wakeel  email:ammarahwakeel9@gmail.com (UET, April 2026)
+//
+// Copyright (C) : 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: Coverage for RVA23U64 profile - Zic64bzicboz extension
+///////////////////////////////////////////////
+
+`define COVER_ZIC64BZICBOZ
+
+covergroup Zic64bzicboz_cg with function sample(ins_t ins);
+    option.per_instance = 0;
+    `include "general/RISCV_coverage_standard_coverpoints.svh"
+
+    cbo_zero: coverpoint ins.current.insn {
+        wildcard bins cbo_zero = {CBO_ZERO};
+    }
+    cbo_zero_offset: coverpoint ins.current.rs1_val[6:0] {
+        bins offset_aligned[] = {[7'd0 : 7'd64]} with (item % 4 == 0);
+    }
+
+    cp_zi64cb: cross cbo_zero, cbo_zero_offset ;
+
+endgroup
+
+function void zic64bzicboz_sample(int hart, int issue, ins_t ins);
+    Zic64bzicboz_cg.sample(ins);
+endfunction

coverpoints/priv/Zic64bzicboz_coverage_init.svh

@@ -0,0 +1,11 @@
+///////////////////////////////////////////////
+// RISC-V Architectural Functional Coverage Covergroups Initialization File
+//
+// Copyright (C) 2026 Harvey Mudd College, 10x Engineers, UET Lahore, Habib University
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+///////////////////////////////////////////////
+
+Zic64bzicboz_cg = new();
+Zic64bzicboz_cg.set_inst_name("obj_Zic64bzicboz");

generators/testgen/src/testgen/priv/extensions/S.py

@@ -126,7 +126,50 @@ def _generate_sstatus_sd_tests(test_data: TestData) -> list[str]:
                             gen_csr_write_sigupd(check_reg, "sstatus", test_data),
                         ]
                     )
+
     lines.append(f"\nCSRW(sstatus, x{save_reg})    # restore CSR")
+
+    lines.extend(
+        [
+            "",
+            "#ifdef SS1P13_SUPPORTED",
+            "#if __riscv_xlen == 64",
+            comment_banner(
+                f"{coverpoint}",
+                "Ss1p13: from S-mode attempt to set sstatus.UXL = 1 and UXL = 2.\n"
+                "UXL=2 must be silently rejected when SXLEN=32 (UXLEN <= SXLEN).",
+            ),
+            f"CSRR(x{save_reg}, sstatus)",
+            "",
+        ]
+    )
+
+    for uxl, label in ((1, "uxlen32"), (2, "uxlen64")):
+        lines.extend(
+            [
+                "",
+                f"# Testcase: Ss1p13 attempt to set sstatus.UXL = {uxl} ({label})",
+                f"CSRR(x{check_reg}, sstatus)                     # read current sstatus into GPR",
+                f"LI(x{reg2}, {~(3 << 32) & 0xFFFFFFFFFFFFFFFF})  # mask to clear UXL bits [33:32]",
+                f"and x{check_reg}, x{check_reg}, x{reg2}         # clear UXL bits [33:32]",
+                f"LI(x{reg2}, {uxl << 32})                        # UXL={uxl} shifted into position [33:32]",
+                f"or x{check_reg}, x{check_reg}, x{reg2}          # OR in desired UXL value",
+                test_data.add_testcase(f"uxl_attempt_{uxl}", coverpoint, covergroup),
+                gen_csr_write_sigupd(check_reg, "sstatus", test_data),
+                f"CSRR(x{check_reg}, sstatus)",  # read back what DUT actually stored
+                write_sigupd(check_reg, test_data),
+            ]
+        )
+
+    lines.extend(
+        [
+            "",
+            f"CSRW(sstatus, x{save_reg})        # restore sstatus after Ss1p13 UXL tests",
+            "#endif // XLEN64",
+            "#endif // SS1P13_SUPPORTED",
+        ]
+    )
+
     test_data.int_regs.return_registers([save_reg, check_reg, reg1, reg2, reg3])
     return lines