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Add ACT4 Configuration for CV32a65x#1176

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jordancarlin merged 28 commits intoriscv:act4from
arshiarifat-10x:cv32a65x-act4
Apr 20, 2026
Merged

Add ACT4 Configuration for CV32a65x#1176
jordancarlin merged 28 commits intoriscv:act4from
arshiarifat-10x:cv32a65x-act4

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davidharrishmc commented Apr 2, 2026 via email

@arshiarifat-10x
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@davidharrishmc becasue in the documentation, in case of CacheSize the unit is explicitly mentioned as in bytes, for LineWidth there are no units which we assume to be in bits (otherwise bytes would have mentioned there too).

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davidharrishmc commented Apr 2, 2026 via email

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@arshiarifat-10x the most recent version of this PR seems to have checked in quite a few files that I assume were not intended to be included (the UDB submodule, multiple generated tests, etc.).

arshiarifat-10x and others added 9 commits April 16, 2026 13:56
…cv#1289)

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Comment thread config/cores/cva6/link.ld
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Comment thread config/cores/cva6/cv32a65x/cv32a65x.yaml
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arshiarifat-10x and others added 3 commits April 20, 2026 12:32
Co-authored-by: Jordan Carlin <jordanmcarlin@gmail.com>
Signed-off-by: arshiarifat-10x <arshia.rifat@10xengineers.ai>
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I would feel more comfortable confirming against the RTL. A 16-byte cache line is unusually small.

On Thu, Apr 2, 2026 at 5:37 AM arshiarifat-10x @.> wrote: arshiarifat-10x left a comment (riscv/riscv-arch-test#1176) <#1176?email_source=notifications&email_token=AR4AA33FDQIHHD3Y2ZCAXUT4TZNITA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTIMJXG42TOMJQGYZKM4TFMFZW63VHNVSW45DJN5XKKZLWMVXHJNLQOJPWG33NNVSW45C7N5YGK3S7MNWGSY3L#issuecomment-4177571062> @davidharrishmc https://github.com/davidharrishmc becasue in the documentation, in case of CacheSize the unit is explicitly mentioned as in bytes, for LineWidth there are no units which we assume to be in bits (otherwise bytes would have mentioned there too). — Reply to this email directly, view it on GitHub <#1176?email_source=notifications&email_token=AR4AA33FDQIHHD3Y2ZCAXUT4TZNITA5CNFSNUABFM5UWIORPF5TWS5BNNB2WEL2JONZXKZKDN5WW2ZLOOQXTIMJXG42TOMJQGYZKM4TFMFZW63VHNVSW45DJN5XKKZLWMVXHJNLQOJPWG33NNVSW45C7N5YGK3S7MNWGSY3L#issuecomment-4177571062>, or unsubscribe https://github.com/notifications/unsubscribe-auth/AR4AA36RRC3J23HGSMNN6ZT4TZNITAVCNFSM6AAAAACXJFNXXOVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHM2DCNZXGU3TCMBWGI . You are receiving this because you were mentioned.Message ID: @.>

@davidharrishmc
The unit has been confirmed directly from the RTL configuration package (cv32a65x_config_pkg.sv and related build config), where both ICacheLineWidth and DCacheLineWidth are defined in bits (128). The downstream RTL usage (division by 8 for byte indexing) further confirms the conversion from bits to bytes, resulting in a 16-byte cache line.

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@arshiarifat-10x Just to confirm, all of the tests are passing on CVA6 now? If so, this looks ready to merge.

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@jordancarlin
yes! All the tests are passing on cva6.

@jordancarlin jordancarlin enabled auto-merge April 20, 2026 13:36
@jordancarlin jordancarlin added this pull request to the merge queue Apr 20, 2026
Merged via the queue into riscv:act4 with commit e128a98 Apr 20, 2026
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