Add exclusive loads and stores#37
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- Add LDXR/LDXRB/LDXRH and LDAXR/LDAXRB/LDAXRH decode and execution. - Add STXR/STXRB/STXRH and STLXR/STLXRB/STLXRH decode and execution. - Refresh Coq snapshots for the exclusive load/store AST and execution paths.
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tperami
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May 27, 2026
| union clause ast = Store : ( | ||
| /* size:*/ range(0,3), reg_index, reg_index, operand, | ||
| /* release */ bool | ||
| /* release */ bool, /* Rs */ option(reg_index) |
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| /* release */ bool, /* Rs */ option(reg_index) | |
| /* release */ bool, /* if exclusive, the target Rs */ option(reg_index) |
| wMem_Addr(addr); | ||
| _PC = _PC + 4; | ||
| wMem(2^size, addr, X(t)[(8*2^size-1)..0], accdesc); | ||
| X(s) = sail_zero_extend(0b0, 64); |
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I'm pretty sure we want the X(s) write to happen before the write to memory, we might want it to be even earlier, but we'll wait test results for that
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Store-exclusive is modeled as a nondeterministic branch in the Sail model. I expect ArchSem to discard the execution branch that is not valid.