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PCI: qcom: Fix Asynchronous SError Interrupt on PCIe #594

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15369e6
PCI: qcom: Add register dump support for PCIe Link Down events
krishnachaitanya-linux Aug 11, 2026
013c952
PCI: qcom: Block accesses to downstream devices on link down
qianyu-qcom Aug 10, 2026
4a59c46
PCI/ERR: Add support for resetting the Root Ports in a platform-speci…
Mani-Sadhasivam Jul 29, 2026
871986b
PCI: host-common: Add link down handling for Root Ports
Mani-Sadhasivam Jul 29, 2026
30a3d1f
PCI: qcom: Implement .reset_root_port() and use for link down
Mani-Sadhasivam Jul 29, 2026
4e90b11
dt-bindings: PCI: qcom: Allow 'global' interrupt for SC8280XP
BigfootACA Aug 15, 2026
1b5cfc7
arm64: dts: qcom: sc8280xp: Add PCIe global interrupts
BigfootACA Aug 15, 2026
3fa2a10
PCI/ERR: serialize hierarchy recovery
BigfootACA Aug 16, 2026
50ad99d
PCI: skip MMIO when the channel is offline
BigfootACA Aug 16, 2026
b6f8ad4
dt-bindings: PCI: qcom: allow Link Down reset
BigfootACA Aug 16, 2026
3fb181f
PCI: qcom: harden Link Down recovery
BigfootACA Aug 16, 2026
1b9acbc
dt-bindings: phy: qcom: allow SC8280XP NOCSR resets
BigfootACA Aug 16, 2026
aefae4c
phy: qcom: qmp-pcie: implement NOCSR reset
BigfootACA Aug 16, 2026
8945f2c
arm64: dts: qcom: add SC8280XP PCIe recovery resets
BigfootACA Aug 16, 2026
74ef185
PCI/AER: avoid config access during shutdown
BigfootACA Aug 16, 2026
49707c3
PCI/PME: stop polling during shutdown
BigfootACA Aug 16, 2026
4b60768
PCI/AER: skip offline devices during error source scan
BigfootACA Aug 16, 2026
e12f60c
PCI: qcom: Limit the ECAM blocker range
BigfootACA Aug 16, 2026
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23 changes: 17 additions & 6 deletions Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -52,11 +52,14 @@ properties:
- const: cnoc_qx # Configuration NoC QX clock

resets:
maxItems: 1
minItems: 1
maxItems: 2

reset-names:
minItems: 1
items:
- const: pci
- const: link_down

required:
- interconnects
Expand All @@ -77,20 +80,26 @@ allOf:
properties:
interrupts:
minItems: 4
maxItems: 4
maxItems: 5
interrupt-names:
minItems: 4
items:
- const: msi0
- const: msi1
- const: msi2
- const: msi3
- const: global
else:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: msi
resets:
maxItems: 1
reset-names:
maxItems: 1

unevaluatedProperties: false

Expand Down Expand Up @@ -149,8 +158,9 @@ examples:
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3";
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
Expand All @@ -170,8 +180,9 @@ examples:

power-domains = <&gcc PCIE_2A_GDSC>;

resets = <&gcc GCC_PCIE_2A_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_2A_BCR>,
<&gcc GCC_PCIE_2A_LINK_DOWN_BCR>;
reset-names = "pci", "link_down";

perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
Expand Down
13 changes: 9 additions & 4 deletions Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -209,6 +209,9 @@ allOf:
- qcom,glymur-qmp-gen4x2-pcie-phy
- qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,kaanapali-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen3x2-pcie-phy
Expand Down Expand Up @@ -265,8 +268,9 @@ examples:

power-domains = <&gcc PCIE_2B_GDSC>;

resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_2B_PHY_BCR>,
<&gcc GCC_PCIE_2B_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
Expand All @@ -292,8 +296,9 @@ examples:

power-domains = <&gcc PCIE_2A_GDSC>;

resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_2A_PHY_BCR>,
<&gcc GCC_PCIE_2A_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
Expand Down
75 changes: 45 additions & 30 deletions arch/arm64/boot/dts/qcom/sc8280xp.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2614,8 +2614,9 @@
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3";
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "global";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
Expand Down Expand Up @@ -2650,8 +2651,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
interconnect-names = "pcie-mem", "cpu-pcie";

resets = <&gcc GCC_PCIE_4_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_4_BCR>,
<&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
reset-names = "pci", "link_down";

power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
Expand Down Expand Up @@ -2689,8 +2691,9 @@

power-domains = <&gcc PCIE_4_GDSC>;

resets = <&gcc GCC_PCIE_4_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_4_PHY_BCR>,
<&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

#clock-cells = <0>;
clock-output-names = "pcie_4_pipe_clk";
Expand Down Expand Up @@ -2726,8 +2729,9 @@
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3";
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "global";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
Expand Down Expand Up @@ -2760,8 +2764,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
interconnect-names = "pcie-mem", "cpu-pcie";

resets = <&gcc GCC_PCIE_3B_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_3B_BCR>,
<&gcc GCC_PCIE_3B_LINK_DOWN_BCR>;
reset-names = "pci", "link_down";

power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
Expand Down Expand Up @@ -2799,8 +2804,9 @@

power-domains = <&gcc PCIE_3B_GDSC>;

resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_3B_PHY_BCR>,
<&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

#clock-cells = <0>;
clock-output-names = "pcie_3b_pipe_clk";
Expand Down Expand Up @@ -2836,8 +2842,9 @@
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3";
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "global";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
Expand Down Expand Up @@ -2870,8 +2877,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
interconnect-names = "pcie-mem", "cpu-pcie";

resets = <&gcc GCC_PCIE_3A_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_3A_BCR>,
<&gcc GCC_PCIE_3A_LINK_DOWN_BCR>;
reset-names = "pci", "link_down";

power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
Expand Down Expand Up @@ -2910,8 +2918,9 @@

power-domains = <&gcc PCIE_3A_GDSC>;

resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_3A_PHY_BCR>,
<&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

qcom,4ln-config-sel = <&tcsr 0xa044 1>;

Expand Down Expand Up @@ -2949,8 +2958,9 @@
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3";
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "global";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
Expand Down Expand Up @@ -2983,8 +2993,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
interconnect-names = "pcie-mem", "cpu-pcie";

resets = <&gcc GCC_PCIE_2B_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_2B_BCR>,
<&gcc GCC_PCIE_2B_LINK_DOWN_BCR>;
reset-names = "pci", "link_down";

power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
Expand Down Expand Up @@ -3022,8 +3033,9 @@

power-domains = <&gcc PCIE_2B_GDSC>;

resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_2B_PHY_BCR>,
<&gcc GCC_PCIE_2B_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

qcom,4ln-config-sel = <&tcsr 0xa044 0>;

Expand Down Expand Up @@ -3061,8 +3073,9 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3";
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3", "global";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
Expand Down Expand Up @@ -3095,8 +3108,9 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
interconnect-names = "pcie-mem", "cpu-pcie";

resets = <&gcc GCC_PCIE_2A_BCR>;
reset-names = "pci";
resets = <&gcc GCC_PCIE_2A_BCR>,
<&gcc GCC_PCIE_2A_LINK_DOWN_BCR>;
reset-names = "pci", "link_down";

power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
Expand Down Expand Up @@ -3135,8 +3149,9 @@

power-domains = <&gcc PCIE_2A_GDSC>;

resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_2A_PHY_BCR>,
<&gcc GCC_PCIE_2A_NOCSR_COM_PHY_BCR>;
reset-names = "phy", "phy_nocsr";

qcom,4ln-config-sel = <&tcsr 0xa044 0>;

Expand Down
9 changes: 9 additions & 0 deletions drivers/pci/controller/dwc/pcie-designware-host.c
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Original file line number Diff line number Diff line change
Expand Up @@ -730,6 +730,9 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
int type, ret;
u32 busdev;

if (READ_ONCE(pp->cfg_access_blocked))
return NULL;

/*
* Checking whether the link is up here is a last line of defense
* against platforms that forward errors on the system bus as
Expand Down Expand Up @@ -824,6 +827,9 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

if (READ_ONCE(pp->cfg_access_blocked))
return NULL;

if (PCI_SLOT(devfn) > 0)
return NULL;

Expand All @@ -838,6 +844,9 @@ static void __iomem *dw_pcie_ecam_conf_map_bus(struct pci_bus *bus, unsigned int
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
unsigned int busn = bus->number;

if (READ_ONCE(pp->cfg_access_blocked))
return NULL;

if (busn > 0)
return pci_ecam_map_bus(bus, devfn, where);

Expand Down
7 changes: 7 additions & 0 deletions drivers/pci/controller/dwc/pcie-designware.h
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Original file line number Diff line number Diff line change
Expand Up @@ -270,6 +270,12 @@

#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc

/* SD-EQ (Gen5 32 GT/s per-lane pre/post cursor equalization) registers */
#define PCIE_RAS_DES_SD_EQ_CONTROL1 0xd0
#define PCIE_RAS_DES_SD_EQ_CONTROL1_LANE_SEL GENMASK(3, 0)
#define PCIE_RAS_DES_SD_EQ_STATUS2 0xe4
#define PCIE_RAS_DES_SD_EQ_STATUS3 0xe8

/* PTM register definitions */
#define PTM_RES_REQ_CTRL 0x8
#define PTM_RES_CCONTEXT_VALID BIT(0)
Expand Down Expand Up @@ -425,6 +431,7 @@ struct dw_pcie_rp {
bool use_imsi_rx:1;
bool keep_rp_msi_en:1;
bool cfg0_io_shared:1;
bool cfg_access_blocked;
u64 cfg0_base;
void __iomem *va_cfg0_base;
u32 cfg0_size;
Expand Down
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