Add ROCm support for CI test_qwen3_4B_ckpt#1621
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tests/e2e/ckpt/test_qwen3_4B_ckpt.py:
Added IS_ROCM detection (os.path.exists("/opt/rocm")) and
if-else conditions in execute() for ROCm-specific args.
Uses async 4+4 mode (4 GPUs train, 4 GPUs rollout) with
train_async.py, --attention-backend auto, optimizer CPU offload,
--sglang-disable-custom-all-reduce, and ROCm env vars.
NVIDIA path remains unchanged.
miles/utils/external_utils/command_utils.py:
Added ROCm NVTE env var cleanup (unset NVTE_FUSED_ATTN,
NVTE_FLASH_ATTN, NVTE_UNFUSED_ATTN) to convert_checkpoint(),
matching the existing cleanup in execute_train().
miles/backends/training_utils/ci_utils.py:
Made KL divergence CI threshold ROCm-conditional: 1e-8 on ROCm
(torch.version.hip), 1e-10 on NVIDIA. ROCm floating point
rounding produces slightly different near-zero values.
miles/backends/megatron_utils/ci_utils.py:
Made peak GPU memory CI threshold ROCm-conditional: 40 GB on
ROCm, 20 GB on NVIDIA. The ROCm config uses TP=1, CP=1 so
each GPU holds the full model (~34 GB vs ~17 GB with TP=2, CP=2).
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Added
IS_ROCMdetection and if-else conditions inexecute()for ROCm-specific args. Uses async 4+4 mode (4 GPUs train, 4 GPUs rollout) withtrain_async.py,--attention-backend auto, optimizer CPU offload,--sglang-disable-custom-all-reduce, and ROCm env vars. NVIDIA path remains unchanged.unset NVTE_FUSED_ATTN,NVTE_FLASH_ATTN,NVTE_UNFUSED_ATTN) toconvert_checkpoint()andexecute_train()incommand_utils.py.ci_utils.py.Related to Miles CI gap Between ROCm & CUDA #1105
Supersedes Add ROCm support for CI test_qwen3_4B_ckpt #1118