Improved TLB flushing logic for Supervisor mode

[ahmadtkhan]

Improved TLB flushing logic for Supervisor mode decreasing the number of Shared TLB accesses, misses, and PTWs.

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This PR addresses #3286 by changing shared TLB flushing for S-stage translation from coarse invalidation to selective invalidation as S-stage flush invalidated the entire shared TLB in the original design. This patch adds selective flush support for the shared TLB using the flushed address and ASID, using similar flush logic of ITLB/DTLB. The implementation uses a small multi-cycle FSM to walk the shared-TLB sets and clear only matching valid entries instead of dropping the whole structure. This reduces over-invalidation in the shared TLB and preserves unrelated translations.

This PR is limited to S-stage flushing. VS-stage and G-stage cases should be added in a few days after they are validated and tested.

[JeanRochCoulon]

To fix Verible, you can run the command which is at the bottom of CONTRIBUTING.md file

[JeanRochCoulon]

Hello, can I ask you to fix Verible ? (just execute the Veribla command on your branch)

[ahmadtkhan]

Hey, sorry for the delay but I completed the PR by adding logic for flush_vvma_i and flush_gvma_i and ran Verible as well.