Implement Svpbmt extension support (parameter, PTE, PTW, CSRs)#3288
Implement Svpbmt extension support (parameter, PTE, PTW, CSRs)#3288StackedArchitect wants to merge 1 commit into
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Implement the RISC-V Svpbmt (Page-Based Memory Types) extension for CVA6, gated behind the new SvpbmtEn configuration parameter. Parameter declaration: - Add SvpbmtEn to cva6_user_cfg_t and cva6_cfg_t in config_pkg.sv - Propagate SvpbmtEn through build_config_pkg.sv - Add SvpbmtEn to all 19 target config packages (enabled in cv64a6_imafdc_sv39 only) PTE field restructuring: - Split pte_cva6_t.reserved[8:0] into pbmt[1:0] (bits [62:61]) and reserved[6:0] (bits [60:54]) - Add pbmt field to tlb_update_cva6_t for TLB refill path CSR control bits (menvcfg/henvcfg.PBMTE): - Add pbmte_d/q and hpbmte_d/q registers in csr_regfile.sv - henvcfg.PBMTE is AND-masked with menvcfg.PBMTE on write - pbmte_o accounts for virtualization mode (v_q) per spec - Thread pbmte signal from CSR through cva6.sv, ex_stage, LSU to MMU PTW validation: - Leaf PTE: fault on reserved encoding (pbmt==2'b11) and when PBMTE disabled - Non-leaf PTE: fault on any non-zero pbmt - When SvpbmtEn=0, non-zero pbmt bits treated as reserved (fault) TLB and MMU output: - Store pbmt in TLB tag struct, output via lu_pbmt_o on hit - Propagate pbmt through shared TLB bypass and SRAM paths - Add lsu_pbmt_o output with registered pipeline in MMU All functionality is strictly gated on CVA6Cfg.SvpbmtEn. Existing configurations with SvpbmtEn=0 are functionally unchanged. Ref: RISC-V Privileged Specification v1.12, Section 12.3
StackedArchitect
requested review from
Jbalkind,
JeanRochCoulon and
cfuguet
as code owners
CI Status NoteThe 2 failing jobs ( All changes in this PR are strictly within The failure is caused by a pre-existing This same issue appears to affect fork-based Happy to re-run CI or address any reviewer feedback. |
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As we need to wait before reviewing the PR, I set the PR as draft. |
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Description
This PR implements the RISC-V Svpbmt (Supervisor Page-Based Memory Types) extension for CVA6, as specified in the RISC-V Privileged Specification v1.12, Section 12.3.
All functionality is introduced behind a new
SvpbmtEnconfiguration parameter. Existing configurations remain functionally unchanged (SvpbmtEn=0by default).This PR is submitted as a complete parameter + functionality unit, following feedback from @JeanRochCoulon on the earlier incremental PRs (#3254, #3269, #3283).
Changes
1. Parameter Declaration
SvpbmtEnadded tocva6_user_cfg_tandcva6_cfg_tinconfig_pkg.svbuild_config_pkg.svbit'(0)by default;bit'(1)incv64a6_imafdc_sv39only)2. PTE Field Restructuring (
cva6_mmu.sv)pte_cva6_t.reserved[8:0]intopbmt[1:0](bits [62:61]) andreserved[6:0](bits [60:54])pbmtfield totlb_update_cva6_tfor the TLB refill path3. CSR Control Bits (
csr_regfile.sv)menvcfg.PBMTE(bit 62): controls Svpbmt enable at M-modehenvcfg.PBMTE(bit 62): AND-masked withmenvcfg.PBMTEon write, ensuring hypervisor isolationpbmte_ooutput accounts for virtualization mode (v_q):menvcfg.PBMTEmenvcfg.PBMTE AND henvcfg.PBMTE4. Signal Threading
pbmtethreaded from CSR regfile throughcva6.sv->ex_stage.sv->load_store_unit.sv->cva6_mmu.sv->cva6_ptw.sv5. PTW Validation (
cva6_ptw.sv)pbmt==2'b11); fault on non-zeropbmtwhen PBMTE disabledpbmt(spec requirespbmt==0for pointer PTEs)SvpbmtEn=0: non-zeropbmtbits are treated as reserved fields and cause page faults6. TLB Storage and MMU Output
cva6_tlb.sv: PBMT stored in TLB tag struct;lu_pbmt_ooutput on hitcva6_shared_tlb.sv: PBMT propagated through bypass and SRAM-backed update pathscva6_mmu.sv:lsu_pbmt_ooutput with registered pipeline (dtlb_pbmt_n/q)Limitations (deferred to future PRs)
lsu_pbmt_ois not yet wired to the cache subsystem (HPDcache backend support)Testing
SvpbmtEn=0for most configurationscv64a6_imafdc_sv39config withSvpbmtEn=1exercises the gated paths via CIRelated