Master candidate verif#3262
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Adds support for Trace Interface or Trace Ingress Port (TIP) on CVA6 TIP is Interface between a RISC-V hart and the trace encoder It generates information about the instruction retired. The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically: Chapter 4.1: Instruction Trace Interface Requirements Chapter 4.2: Instruction Trace Interface The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump. What I have been able to test so far: Simulation: Executed C binaries and observed the waveform of TIP. --------- Co-authored-by: root <darshak.sheladiya@sysgo.com> Co-authored-by: CHAUVON Guillaume <guillaume.chauvon@thalesgroup.com> Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Integration of instr_tracing in corev_apu --------- Co-authored-by: ALLART Come <come.allart@thalesgroup.com> Co-authored-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com> Co-authored-by: Coulon Jean Roch <jean-roch.coulon@thalesgroup.com>
Ref: openhwgroup#3185 --------- Co-authored-by: Alex Chen <alexchenic@users.noreply.github.com> Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
AngelaGonzalezMarino
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Jbalkind,
JeanRochCoulon and
zarubaf
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Continuation of #3261
Added verification scripts and configurations used