Master candidate update pipeline buses and cache subsystem

.github/workflows/verible.yml

@@ -20,4 +20,5 @@ jobs:
       - uses: chipsalliance/verible-formatter-action@main
         with:
           github_token: ${{ secrets.GITHUB_TOKEN }}
-          files: '$(find core -regex ".*\.\(v\|sv\)$" | grep -v "^core/include/.*_config_pkg.sv$")'
+          files: '$(find core -regex ".*\.\(v\|sv\)$" | grep -v "^core/include/.*_config_pkg\.sv$")'
+          fail_on_formatting_suggestions: true

.gitlab-ci.yml

@@ -227,6 +227,21 @@ smoke-hwconfig:
     - when: manual
       allow_failure: true
 
+it-test:
+  extends:
+    - .synthesis_test
+  variables:
+    DASHBOARD_JOB_TITLE: "Instruction Trace test"
+    DASHBOARD_JOB_DESCRIPTION: "Test to Challenge the Hardware flow of the Instruction Tracer"
+    DASHBOARD_SORT_INDEX: 0
+    DASHBOARD_JOB_CATEGORY: "Basic"
+    DV_SIMULATORS: "vcs-testharness"
+  script:
+    - python3 .gitlab-ci/scripts/report_fail.py
+    - bash verif/regress/Instr_tracing_test.sh ../tests/custom/ITI/test_iti_asm.o
+    - python3 .gitlab-ci/scripts/report_pass.py
+    - cp -r verif/sim/Instr_tracing_artifact artifacts/
+
 spyglass:
   extends:
     - .synthesis_test

Makefile

@@ -160,15 +160,16 @@ src :=  $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
         $(if $(spike-tandem),verif/tb/core/uvmc_rvfi_reference_model_pkg.sv)         \
         $(if $(spike-tandem),verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv)              \
         $(if $(spike-tandem),corev_apu/tb/common/spike.sv)                           \
-        corev_apu/src/ariane.sv                                                      \
+        core/cva6_rvfi.sv                                                            \
+		corev_apu/src/ariane.sv                                                      \
         $(wildcard corev_apu/bootrom/*.sv)                                           \
         $(wildcard corev_apu/clint/*.sv)                                             \
         $(wildcard corev_apu/fpga/src/axi2apb/src/*.sv)                              \
         $(wildcard corev_apu/fpga/src/apb_timer/*.sv)                                \
         $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv)                            \
         $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv)                         \
         $(wildcard corev_apu/axi_mem_if/src/*.sv)                                    \
-				$(wildcard corev_apu/riscv-dbg/src/*.sv)                                   \
+        $(wildcard corev_apu/riscv-dbg/src/*.sv)                                     \
         corev_apu/rv_plic/rtl/rv_plic_target.sv                                      \
         corev_apu/rv_plic/rtl/rv_plic_gateway.sv                                     \
         corev_apu/rv_plic/rtl/plic_regmap.sv                                         \
@@ -200,13 +201,34 @@ src :=  $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
         vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv  \
         vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv     \
         vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv                    \
+        corev_apu/instr_tracing/ITI/include/iti_pkg.sv                               \
+        corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv                     \
+        corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv        \
         corev_apu/tb/ariane_testharness.sv                                           \
         corev_apu/tb/ariane_peripherals.sv                                           \
         corev_apu/tb/rvfi_tracer.sv                                                  \
         corev_apu/tb/common/uart.sv                                                  \
         corev_apu/tb/common/SimDTM.sv                                                \
-        corev_apu/tb/common/SimJTAG.sv
-
+        corev_apu/tb/common/SimJTAG.sv                                               \
+        corev_apu/instr_tracing/ITI/cva6_iti/iti.sv                                  \
+        corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv                     \
+        corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv                    \
+        corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv                       \
+        vendor/pulp-platform/common_cells/src/counter.sv                             \
+        vendor/pulp-platform/common_cells/src/sync.sv                                \
+        vendor/pulp-platform/common_cells/src/sync_wedge.sv                          \
+        vendor/pulp-platform/common_cells/src/edge_detect.sv                         \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv                            \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv                  \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv                      \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv              \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv                    \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv                         \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv              \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv                      \
+        vendor/pulp-platform/common_cells/src/fifo_v3.sv                             \
+        corev_apu/instr_tracing/DPTI/slicer_DPTI.sv                                  \
+        corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv
 src := $(addprefix $(root-dir), $(src))
 
 copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \
@@ -216,6 +238,9 @@ copro_src := $(addprefix $(root-dir), $(copro_src))
 uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/vhdl_orig/*.vhd)
 uart_src := $(addprefix $(root-dir), $(uart_src))
 
+dpti_src := $(wildcard corev_apu/instr_tracing/DPTI/*.vhd)
+dpti_src := $(addprefix $(root-dir), $(dpti_src))
+
 uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv     \
               corev_apu/fpga/src/apb_uart/src/slib_counter.sv       \
               corev_apu/fpga/src/apb_uart/src/slib_edge_detect.sv   \
@@ -311,6 +336,7 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
           $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \
           $(CVA6_REPO_DIR)/verif/tb/core/ \
           $(CVA6_REPO_DIR)/core/include/ \
+          $(CVA6_REPO_DIR)/corev_apu/instr_tracing/ITI/include \
           $(SPIKE_INSTALL_DIR)/include/disasm/
 
 # Compile and sim flags
@@ -784,9 +810,10 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co
 src/bootrom/bootrom_$(XLEN).sv:
 	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv
 
-fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
+fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(dpti_src) $(src_flist)
 	@echo "[FPGA] Generate sources"
 	@echo read_vhdl        {$(uart_src)}    > corev_apu/fpga/scripts/add_sources.tcl
+	@echo read_vhdl        {$(dpti_src)}   >> corev_apu/fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src_flist))}		>> corev_apu/fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} 	   >> corev_apu/fpga/scripts/add_sources.tcl

README.md

@@ -60,55 +60,10 @@ bash verif/regress/smoke-tests.sh
 
 Simulating the CVA6 is done by using `verif/sim/cva6.py`.
 
-The environment variable `DV_SIMULATORS` allows you to specify which simulator to use.
-
-Four simulation types are supported:
-- **veri-testharness**: verilator with corev_apu/testharness testbench
-- **vcs-testharness**: vcs with corev_apu/testharness testbench
-- **vcs-uvm**: vcs with UVM testbench
-- **Spike** ISS 
-
-You can set several simulators, such as :
-
-```sh
-export DV_SIMULATORS=veri-testharness,vcs-testharness,vcs_uvm
-```
-
-If exactly 2 simulators are given, their trace is compared ([see the Regression tests section](#running-regression-tests-simulations)).
-
-Here is how you can run the hello world C program with the Verilator model: 
-
-```sh
-# Make sure to source this script from the root directory 
-# to correctly set the environment variables related to the tools
-source verif/sim/setup-env.sh
-
-# Set the NUM_JOBS variable to increase the number of parallel make jobs
-# export NUM_JOBS=
-
-export DV_SIMULATORS=veri-testharness
-
-cd ./verif/sim
-
-python3 cva6.py --target cv32a60x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml \
---c_tests ../tests/custom/hello_world/hello_world.c \
---linker=../../config/gen_from_riscv_config/linker/link.ld \
---gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib \
--nostartfiles -g ../tests/custom/common/syscalls.c \
-../tests/custom/common/crt.S -lgcc \
--I../tests/custom/env -I../tests/custom/common"
-```
-
-You can run either assembly programs (check `verif/test/custom/hello_world/custom_test_template.S`) or C programs. Run `python3 cva6.py --help` to have more informations on the available parameters.
-
-## Simulating with VCS and Verdi
-
-You can set the environment variable `VERDI` as such if you want to launch Verdi while simulating with VCS:
-
-```sh
-export VERDI=1
-```
-
+* **[Running Simulations](tutorials/running_sim.md)**
+* **[ASIC Implementation](tutorials/asic.md)**
+* **[FPGA Implementation and running an OS](tutorials/fpga.md)**
+* **[Instruction Tracing](corev_apu/instr_tracing/README.md)**
 
 # Running regression tests simulations
 

common/local/util/instr_trace_item.svh

@@ -41,6 +41,8 @@ class instr_trace_item #(
     logic              result_fpr [$];
     logic [63:0]       imm;
     logic [63:0]       result;
+    logic              dest_we_valid;
+    logic              dest_is_fp;
     logic [CVA6Cfg.PLEN-1:0]       paddr;
     string             priv_lvl;
     bp_resolve_t       bp;
@@ -49,14 +51,16 @@ class instr_trace_item #(
 
     // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information
     function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32],
-                logic [63:0] fp_reg_file [32], logic [63:0] result, logic [CVA6Cfg.PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
+                logic [63:0] fp_reg_file [32], logic [63:0] result, logic dest_we_valid, logic dest_is_fp, logic [CVA6Cfg.PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp);
         this.simtime  = simtime;
         this.cycle    = cycle;
         this.pc       = sbe.pc;
         this.sbe      = sbe;
         this.gp_reg_file = gp_reg_file;
         this.fp_reg_file = fp_reg_file;
         this.result   = result;
+        this.dest_we_valid = dest_we_valid;
+        this.dest_is_fp = dest_is_fp;
         this.paddr    = paddr;
         this.bp       = bp;
         this.priv_lvl = (debug_mode) ? "D" : getPrivLevel(priv_lvl);
@@ -195,6 +199,68 @@ class instr_trace_item #(
         endcase
     endfunction
 
+    function logic scoreboardDestIsFp();
+        if (sbe.fu inside {ariane_pkg::FPU, ariane_pkg::FPU_VEC}) begin
+            return ariane_pkg::fd_changes_rd_state(sbe.op);
+        end
+        return ariane_pkg::is_rd_fpr(sbe.op);
+    endfunction
+
+    function logic rawDestIsFp();
+        if (dest_we_valid) begin
+            return dest_is_fp;
+        end
+        return scoreboardDestIsFp();
+    endfunction
+
+    function logic fpInstrForcesGprDest();
+        logic [6:0] opcode = instr[6:0];
+        logic [4:0] funct5 = instr[31:27];
+        logic [2:0] rm     = instr[14:12];
+
+        if (opcode == riscv::OpcodeOpFp) begin
+            if (funct5 == 5'b11000) begin
+                // fcvt.*.* instructions that target an integer register
+                return 1'b1;
+            end
+
+            if (funct5 == 5'b10100) begin
+                // fle.*, flt.*, feq.* comparisons produce integer results.
+                return 1'b1;
+            end
+
+            if (funct5 == 5'b11100) begin
+                // fmv.x.* (rm == 000) and fclass (rm == 001) always write GPRs.
+                if ((rm == 3'b000) || (rm == 3'b001)) begin
+                    return 1'b1;
+                end
+                // Alternate encodings when FP16ALT is enabled mirror rm encodings.
+                if (CVA6Cfg.XF16ALT && ((rm == 3'b100) || (rm == 3'b101))) begin
+                    return 1'b1;
+                end
+            end
+        end
+
+        return 1'b0;
+    endfunction
+
+    function logic effectiveDestIsFp();
+        logic dest_is_fp_raw = rawDestIsFp();
+
+        if (fpInstrForcesGprDest()) begin
+            return 1'b0;
+        end
+
+        return dest_is_fp_raw;
+    endfunction
+
+    function void adjustResultRegKinds();
+        logic final_dest_is_fp = effectiveDestIsFp();
+        foreach (result_fpr[i]) begin
+            result_fpr[i] = final_dest_is_fp;
+        end
+    endfunction
+
     function string printInstr();
         string s;
 
@@ -379,6 +445,8 @@ class instr_trace_item #(
         //                                      instr,
         //                                      s);
 
+        adjustResultRegKinds();
+
         foreach (result_regs[i]) begin
             if (result_fpr[i])
                 s = $sformatf("%s %-4s:%16x", s, fpRegAddrToStr(result_regs[i]), this.result);
@@ -466,45 +534,48 @@ class instr_trace_item #(
 
     function string printRFBCInstr(input string mnemonic, input bit use_rnd);
 
+        logic dest_fp = effectiveDestIsFp();
         result_regs.push_back(rd);
-        result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op));
+        result_fpr.push_back(dest_fp);
         read_regs.push_back(rs2);
         read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op));
         read_regs.push_back(sbe.result[4:0]);
         read_fpr.push_back(ariane_pkg::is_imm_fpr(sbe.op));
 
         if (use_rnd && instr[14:12]!=3'b111)
-            return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]), fpRmToStr(instr[14:12]));
+            return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]), fpRmToStr(instr[14:12]));
         else
-            return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]));
+            return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), ariane_pkg::is_imm_fpr(sbe.op)?fpRegAddrToStr(sbe.result[4:0]):regAddrToStr(sbe.result[4:0]));
     endfunction // printRFInstr
 
     function string printRFInstr(input string mnemonic, input bit use_rnd);
 
+        logic dest_fp = effectiveDestIsFp();
         result_regs.push_back(rd);
-        result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op));
+        result_fpr.push_back(dest_fp);
         read_regs.push_back(rs1);
         read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op));
         read_regs.push_back(rs2);
         read_fpr.push_back(ariane_pkg::is_rs2_fpr(sbe.op));
 
         if (use_rnd && instr[14:12]!=3'b111)
-            return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), fpRmToStr(instr[14:12]));
+            return $sformatf("%-12s %4s, %s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2), fpRmToStr(instr[14:12]));
         else
-            return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2));
+            return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), ariane_pkg::is_rs2_fpr(sbe.op)?fpRegAddrToStr(rs2):regAddrToStr(rs2));
     endfunction // printRFInstr
 
     function string printRFInstr1Op(input string mnemonic, input bit use_rnd);
 
+        logic dest_fp = effectiveDestIsFp();
         result_regs.push_back(rd);
-        result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op));
+        result_fpr.push_back(dest_fp);
         read_regs.push_back(rs1);
         read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op));
 
         if (use_rnd && instr[14:12]!=3'b111)
-            return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), fpRmToStr(instr[14:12]));
+            return $sformatf("%-12s %4s, %s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1), fpRmToStr(instr[14:12]));
         else
-            return $sformatf("%-12s %4s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), ariane_pkg::is_rd_fpr(sbe.op)?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1));
+            return $sformatf("%-12s %4s, %s", $sformatf("%s.%s",mnemonic, fpFmtToStr(instr[26:25])), dest_fp?fpRegAddrToStr(rd):regAddrToStr(rd), ariane_pkg::is_rs1_fpr(sbe.op)?fpRegAddrToStr(rs1):regAddrToStr(rs1));
     endfunction // printRFInstr1Op
 
     function string printR4Instr(input string mnemonic);
@@ -523,8 +594,9 @@ class instr_trace_item #(
 
     function string printFpSpecialInstr();
 
+        logic dest_fp = effectiveDestIsFp();
         result_regs.push_back(rd);
-        result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op));
+        result_fpr.push_back(dest_fp);
         read_regs.push_back(rs1);
         read_fpr.push_back(ariane_pkg::is_rs1_fpr(sbe.op));
 
@@ -634,8 +706,9 @@ class instr_trace_item #(
     endfunction // printCSRInstr
 
     function string printLoadInstr(input string mnemonic);
+        logic dest_fp = effectiveDestIsFp();
         result_regs.push_back(rd);
-        result_fpr.push_back(ariane_pkg::is_rd_fpr(sbe.op));
+        result_fpr.push_back(dest_fp);
         read_regs.push_back(rs1);
         read_fpr.push_back(1'b0);
         // save the immediate for calculating the virtual address
@@ -723,4 +796,4 @@ class instr_trace_item #(
         return this.printRInstr(s);
     endfunction
   endclass
-`endif
+`endif