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Fix/ghidra gcc aarch64 switch and http docs - #9680
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Nishant1600 wants to merge 3 commits into
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Nishant1600 wants to merge 3 commits into
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The CLI guide shows `rea mcp --http --host 0.0.0.0` and the matching `environment-serve` example, and explains the Host/Origin 403 checks, but the warning that these endpoints have no TLS or client authentication lived only in the MCP contract reference. A reader could take `--allowed-hosts` or `MCP_ALLOWED_HOSTS` for access control; it only guards against DNS rebinding and cross-origin browser pages. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01FZXWdmycjdemfBYLDTuc6r
REA's AArch64 relative jump-table recovery matched only the shifted-register dispatch ADD that clang emits (`add xD, xN, xM, lsl morluto#2`). GCC's aarch64_output_casesi loads the entry zero-extended with LDRB/LDRH and sign-extends it in an extended-register ADD (`add x1, x0, w1, sxtb morluto#2` or `sxth morluto#2`), so the matcher returned null and GCC-built tables kept their table source and case labels unknown. Accept the SXTB/SXTH extended-register form with the existing 0/2 scales. The extend must read exactly the loaded width and makes the entries signed; X-register extends, SXTW word tables and other scales are still refused. The recovered record keeps the extend so the jump-table evidence names the real dispatch instead of `LSL morluto#2`. Add relative-switch-gcc.S, which shares relative-switch.S's symbol and case oracle, places one case before the ADR label so its entry is negative, and runs in the AArch64 jump-table lane for byte and halfword entries. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01FZXWdmycjdemfBYLDTuc6r
Match LSL, SXTB and SXTH in one operator group and record that operator for the jump-table evidence, instead of separate shift and extend groups. Drop the W-register check on the extended source: SXTB/SXTH read only the low byte or halfword whatever the register is named, and Ghidra's ADD (extended register) constructor always prints Rm as a W register. Evidence text for clang's shifted-register forms is unchanged. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01FZXWdmycjdemfBYLDTuc6r
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Summary
Problem and expected behavior
Change and scope
Follow the contribution scope.
Unresolved scope, authority, side effects, or required verification block
integration. Link the required maintainer scope decision for new providers or
capabilities involving target execution, injection, mutation, or protection
recovery; ordinary fixes within existing boundaries may state "not applicable".
Draft PRs may leave the scope decision pending and the readiness and merge checklists
unchecked. Maintainers can help resolve open questions.
Contract and boundary impact
docs/public/product-catalog.json), package, or installation impact (CI generates and validates ignored catalogs andskills/; edit authored instructions in.agents/skills/reverse-engineer-anything/and never commit build outputs):Expected effects (check known effects; use documentation-only on its own).
Unchecked items do not establish absence; leave uncertainties visible.
Evidence and regression coverage
For boundary fixes, identify the applicable boundary regressions
and lifecycle regressions
covered by the evidence above, and explain relevant gaps.
For evidence-bearing changes:
Validation performed
command— resultCompatibility, safety, and release
Author readiness
Human owner:
Before merge
type(scope): outcome.