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1 change: 1 addition & 0 deletions Cargo.lock
Original file line number Diff line number Diff line change
Expand Up @@ -5120,6 +5120,7 @@ version = "0.0.0"
dependencies = [
"aarch64defs",
"arrayvec",
"bitfield-struct 0.10.1",
"cfg-if",
"crc32fast",
"fdt",
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1 change: 1 addition & 0 deletions openhcl/openhcl_boot/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ rust-version.workspace = true

[dependencies]
aarch64defs.workspace = true
bitfield-struct.workspace = true
minimal_rt.workspace = true
underhill_confidentiality.workspace = true
host_fdt_parser.workspace = true
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5 changes: 5 additions & 0 deletions openhcl/openhcl_boot/src/arch/aarch64/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,17 @@ mod memory;
mod vp;
mod vsm;

use crate::host_params::shim_params::ShimParams;
pub use memory::physical_address_bits;
pub use memory::setup_vtl2_memory;
pub use memory::verify_imported_regions_hash;
pub use vp::setup_vtl2_vp;
pub use vsm::get_isolation_type;

pub fn initialize(_: &ShimParams) {}

pub fn uninitialize(_: &ShimParams) {}

// Entry point.
#[cfg(minimal_rt)]
core::arch::global_asm! {
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18 changes: 9 additions & 9 deletions openhcl/openhcl_boot/src/arch/x86_64/address_space.rs
Original file line number Diff line number Diff line change
Expand Up @@ -25,21 +25,21 @@ use zerocopy::FromBytes;
use zerocopy::IntoBytes;
use zerocopy::KnownLayout;

const X64_PTE_PRESENT: u64 = 1;
const X64_PTE_READ_WRITE: u64 = 1 << 1;
const X64_PTE_ACCESSED: u64 = 1 << 5;
pub const X64_PTE_PRESENT: u64 = 1;
pub const X64_PTE_READ_WRITE: u64 = 1 << 1;
pub const X64_PTE_ACCESSED: u64 = 1 << 5;
const X64_PTE_DIRTY: u64 = 1 << 6;
const X64_PTE_LARGE_PAGE: u64 = 1 << 7;
const X64_PTE_CONFIDENTIAL: u64 = 1 << 51;
pub const X64_PTE_CONFIDENTIAL: u64 = 1 << 51;

const PAGE_TABLE_ENTRY_COUNT: usize = 512;
pub const PAGE_TABLE_ENTRY_COUNT: usize = 512;

const X64_PAGE_SHIFT: u64 = 12;
const X64_PTE_BITS: u64 = 9;
pub const X64_PAGE_SHIFT: u64 = 12;
pub const X64_PTE_BITS: u64 = 9;

#[derive(Debug, IntoBytes, KnownLayout, FromBytes)]
#[repr(transparent)]
struct PageTableEntry {
pub struct PageTableEntry {
entry: AtomicU64,
}
#[derive(Debug, Copy, Clone)]
Expand Down Expand Up @@ -117,7 +117,7 @@ impl PageTableEntry {

#[repr(C)]
#[derive(Debug, IntoBytes, KnownLayout, FromBytes)]
struct PageTable {
pub struct PageTable {
entries: [PageTableEntry; PAGE_TABLE_ENTRY_COUNT],
}

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13 changes: 13 additions & 0 deletions openhcl/openhcl_boot/src/arch/x86_64/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ mod vp;
mod vsm;

use crate::host_params::shim_params::IsolationType;
use crate::host_params::shim_params::ShimParams;
pub use address_space::TdxHypercallPage;
pub use memory::setup_vtl2_memory;
pub use memory::verify_imported_regions_hash;
Expand All @@ -40,6 +41,18 @@ pub fn physical_address_bits(isolation: IsolationType) -> u8 {
}
}

pub fn initialize(p: &ShimParams) {
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these need comments on what the intention of these are for, since i assume for CCA we will need to probably do something similar. We need to document what the requirements for arch:: etc calls are.

if p.isolation_type == IsolationType::Snp {
snp::Ghcb::initialize();
}
}

pub fn uninitialize(p: &ShimParams) {
if p.isolation_type == IsolationType::Snp {
snp::Ghcb::uninitialize();
}
}

// Entry point.
#[cfg(minimal_rt)]
core::arch::global_asm! {
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