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[xbar_peri,dv] V1 sign-off checklist #573

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46 changes: 24 additions & 22 deletions doc/proj/stages.md
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Expand Up @@ -10,28 +10,30 @@ Slight modification to the stages and checklists were made to meet the requireme

This table shows the current design and verification stage for each block in Mocha.

| **Block name** | **Design stage** | **Verification stage** |
|-------------------|------------------|------------------------|
| AXI crossbar | D0 | V0 |
| Clock manager | D0 | V0 |
| CVA6-CHERI | D0 | V0 |
| Debug module | D0 | V0 |
| Entropy source | D0 | V0 |
| GPIO | D0 | V0 |
| I2C | D0 | V0 |
| KMAC | D0 | V0 |
| Mailbox | D0 | V0 |
| PLIC | D0 | V0 |
| Power manager | D0 | V0 |
| Reset manager | D0 | V0 |
| ROM control | D0 | V0 |
| SPI device | D0 | V0 |
| SPI host | D0 | V0 |
| SRAM | D0 | V0 |
| Tag controller | D0 | V0 |
| TileLink crossbar | D0 | V0 |
| Timer | D0 | V0 |
| UART | D0 | V0 |
| **Block name** | **Design stage** | **Verification stage** |
|-----------------------|------------------|------------------------|
| AXI crossbar | D0 | V0 |
| Clock manager | D0 | V0 |
| CVA6-CHERI | D0 | V0 |
| Debug module | D0 | V0 |
| Entropy source | D0 | V0 |
| GPIO | D0 | V0 |
| I2C | D0 | V0 |
| KMAC | D0 | V0 |
| Mailbox | D0 | V0 |
| PLIC | D0 | V0 |
| Power manager | D0 | V0 |
| Reset manager | D0 | V0 |
| ROM control | D0 | V0 |
| SPI device | D0 | V0 |
| SPI host | D0 | V0 |
| SRAM | D0 | V0 |
| Tag controller | D0 | V0 |
| [TileLink crossbar][] | D0 | V1 |
| Timer | D0 | V0 |
| UART | D0 | V0 |

[TileLink crossbar]: xbar_peri.md

## Sign-off procedure

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57 changes: 57 additions & 0 deletions doc/proj/xbar_peri.md
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# XBAR_PERI Checklist

This checklist covers the [Design and verification stages](stages.md#design-and-verification-stages) sign-off for the `xbar_peri` block.

This block has been vendored-in from [OpenTitan](https://github.com/lowRISC/opentitan) project.
`xbar_peri` is auto-generated by `tlgen.py` from `hw/top_chip/ip/xbar_peri/data/`.
It connects one host (CVA6-CHERI) to multiple peripheral devices over TileLink-UL: ROM, Entropy Source, KMAC, PLIC, Timer, GPIO, I2C, SPI device, SPI host, UART and Managers (Clock, Reset and Power).
The testbench reuses the generic TLUL XBAR DV infrastructure from [`hw/vendor/lowrisc_ip/ip/tlul/`](../../hw/vendor/lowrisc_ip/ip/tlul/doc/dv/README.md).

## Design Checklist

*TODO*


## Verification Checklist

### V1

All checklist items refer to the [V1 verification sign-off checklist](stages.md#v1-verification-sign-off-checklist).

To run V1 tests locally:
```
dvsim hw/top_chip/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson -i V1
```

Type | Item | Resolution | Note/Collaterals
--------------|----------------------------------|------------|------------------
Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [TLUL XBAR DV doc][]
Documentation | [TESTPLAN_COMPLETED][] | Done | [TLUL testplan][]
Review | [DESIGN_SPEC_REVIEWED][] | Waived | xbar_peri comes from OpenTitan where the specification was reviewed as part of the OpenTitan design process; no significant modifications made for Mocha, so waived for V1 in Mocha.
Review | [TESTPLAN_REVIEWED][] | Done |
Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Waived | TLUL socket primitives (`tlul_socket_1n`, `tlul_socket_m1`) sourced from `lowrisc_ip` vendor library, carried as pre-verified at V2 in OpenTitan per `hw/ip/tlul/data/tlul.prj.hjson`. `prim_arbiter` waived, consistent with OpenTitan V1 precedent.
Integration | [TB_DUT_CONNECTED][] | Done | DUT instantiated in `hw/top_chip/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv` with all 12 TL interfaces connected
Simulation | [SIM_COVERAGE_MODEL_ADDED][] | Done | Coverage model is defined in `mocha/hw/vendor/lowrisc_ip/ip/tlul/generic_dv/env/xbar_env_cov.sv`
Simulation | [SIM_ASSERTIONS_ADDED][] | Done | <ul><li>X/unknown checks on TL channel signals provided in `tlul_assert.sv`</li><li>TLUL protocol assertions bound in `xbar_peri_bind.sv` for all interfaces</li></ul>
Simulation | [SIM_SMOKE_TEST_PASSING][] | Done | `xbar_smoke`: 50/50 passed (100%) --> nightly 2026-05-20 based on commit `d051a93`
Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | Smoke regression defined in `hw/top_chip/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson` and added to the aggregate `mocha/hw/top_chip/dv/mocha_sim_cfgs.hjson` file used for nightly/weekly CI regressions.
Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | Nightly CI running on `main` and results are available at the [COSMIC reports dashboard](https://cosmic-project.lowrisc.org/reports)
Formal | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | xbar_peri verified by simulation only; no FPV flow
Regression | [FPV_REGRESSION_SETUP][] | N/A | No FPV for xbar_peri

[TLUL XBAR DV doc]: ../../hw/vendor/lowrisc_ip/ip/tlul/doc/dv/README.md
[TLUL testplan]: ../../hw/vendor/lowrisc_ip/ip/tlul/data/tlul_testplan.hjson

[DV_DOC_DRAFT_COMPLETED]: stages.md#v1-verification-sign-off-checklist
[TESTPLAN_COMPLETED]: stages.md#v1-verification-sign-off-checklist
[PRE_VERIFIED_SUB_MODULES_V1]: stages.md#v1-verification-sign-off-checklist
[DESIGN_SPEC_REVIEWED]: stages.md#v1-verification-sign-off-checklist
[TESTPLAN_REVIEWED]: stages.md#v1-verification-sign-off-checklist
[SIM_SMOKE_TEST_PASSING]: stages.md#v1-verification-sign-off-checklist
[TB_DUT_CONNECTED]: stages.md#v1-verification-sign-off-checklist
[SIM_ASSERTIONS_ADDED]: stages.md#v1-verification-sign-off-checklist
[SIM_COVERAGE_MODEL_ADDED]: stages.md#v1-verification-sign-off-checklist
[SIM_SMOKE_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist
[SIM_NIGHTLY_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist
[FPV_MAIN_ASSERTIONS_PROVEN]: stages.md#v1-verification-sign-off-checklist
[FPV_REGRESSION_SETUP]: stages.md#v1-verification-sign-off-checklist