[chip, I2C, DV] Top level I2C host test#473
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requested review from
elliotb-lowrisc,
marnovandermaas and
martin-velay
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Taking the transfer checking part out from the i2c_read_byte() and i2c_write_byte() functions. It is needed when you want to controller wants to read / write multiple bytes. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
This is suggested in programmer's guide. As a precautionary step, reset the FMT fifo before sending any transfer Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
…depth Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
It takes care that the resultant SCL high cycles must satisfy below
equations:
** scl_high_cycles >= 4 (to support correct function in clock
streching)
** scl_high_cycles = scl_period_cycles - (rise_cycles + fall_cycles
+ scl_low_cycles)
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
OT's I2C block supports Standard, Fast and Fast Plus modes. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
Controller writes multiple bytes to the target's receiver and then reads multiple bytes from the same address. At the end of both read and write transfer, the test checks if the transfer was succesful. If yes, then the test compares all the read bytes with the data bytes that was sent as part of write transfer. Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
This vseq: ** reads the SW symbols to get the timing values ** calculates relevant timing parameter use by the agent to send Ack, Nack and Rdata. ** start the reactive sequence Signed-off-by: Kinza Qamar <kqzaman@lowrisc.org>
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Close #507