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[PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC #199733

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[PowerPC]Avoid combine to ADDC i8 or ADDC i16 for PPCTargetLowering::combineSignExtendSetCC #199733

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11 changes: 8 additions & 3 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15873,7 +15873,7 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
return SDValue();

SDValue N0 = N->getOperand(0);
if (N0.getOpcode() != ISD::SETCC)
if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse())
return SDValue();

ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Expand All @@ -15889,16 +15889,21 @@ SDValue PPCTargetLowering::combineSignExtendSetCC(SDNode *N,
SDValue X = isNullConstant(LHS) ? RHS : LHS;
EVT XVT = X.getValueType(); // The type of x in the setcc x, 0, eq.

if (XVT != MVT::i32 && XVT != MVT::i64)
return SDValue();

if ((XVT == MVT::i64 || VT == MVT::i64) && !Subtarget.isPPC64())
return SDValue();

// On PPC64, i32 carry operations use the full 64-bit XER register,
// so we must use i64 operations to avoid incorrect results.
// Use i64 operations and truncate the result if needed.
if (XVT != MVT::i64 && Subtarget.isPPC64())
if (XVT != MVT::i64 && Subtarget.isPPC64()) {
if (!X.hasOneUse())
return SDValue();
// Zero-extend if input type is not 64bits.
X = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, X);

}
EVT OpVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;

// Generate: SUBFE(ADDC(X, -1)).
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testComparesieqsc.ll
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Expand Up @@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 56
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testComparesieqss.ll
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Expand Up @@ -100,14 +100,14 @@ define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 48
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testCompareslleqsc.ll
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Expand Up @@ -100,14 +100,14 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsc_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 56
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqsc_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 56
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/testCompareslleqss.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -99,14 +99,14 @@ define i64 @test_lleqss_sext_z(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqss_sext_z:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: clrldi r3, r3, 48
; CHECK-BE-NEXT: clrldi r3, r3, 32
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_lleqss_sext_z:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: clrldi r3, r3, 48
; CHECK-LE-NEXT: clrldi r3, r3, 32
; CHECK-LE-NEXT: addic r3, r3, -1
; CHECK-LE-NEXT: subfe r3, r3, r3
; CHECK-LE-NEXT: blr
Expand Down