[ExportVerilog] Add a lowering option for always emitting begin/end#10563
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uenoku wants to merge 2 commits into
Open
[ExportVerilog] Add a lowering option for always emitting begin/end#10563uenoku wants to merge 2 commits into
uenoku wants to merge 2 commits into
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There is a request to always emit begin/end for statements regardless of its content to improve the
stability of the output verilog.
I also think it might make sense to make this simply default and remove begin/end omission since it increased the complexity of ExportVerilog a bit.
Assisted-by: claude code: sonnet 4.6