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[Moore][Sim][SV] Add $strobe[boh] lowering via sim.defer#10556

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[Moore][Sim][SV] Add $strobe[boh] lowering via sim.defer#10556
VecoMr wants to merge 1 commit into
llvm:mainfrom
VecoMr:import-verilog-add-strobe

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@VecoMr
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@VecoMr VecoMr commented May 28, 2026

Implement the SV $strobe[boh]system tasks.

  • Add moore.builtin.strobe op in the Moore dialect to represent $strobe[boh].
  • Add sim.deferop in the Sim dialect: a procedural region who schedules its body in the postponed region. Underlying primitive for $strobe, $fstrobe, $monitor, and VHDL postponed processes.
  • Add StrobeBIOpConverion in MooreTocore lowering.
  • Add sv.strobe op to SV dialect, analogous to sv.write and wire it in SVVisitors.h and ExportVerilog to emit $strobe(...)
  • Extend lowerPrintFormattedProcToSVin SimToSV to detect sim.proc.print inside sim.defer, and emit sv.strobe.
  • Add tests for each stage of the pipeline.

Implement the SV `\$strobe[boh]`system tasks.
- Add `moore.builtin.strobe` op in the Moore dialect to represent `$strobe[boh]
- Add `sim.defer`op in the Sim dialect: a procedural region who schedules its body in the postponed region. Underlying primitive for `$strobe`, `$fstrobe`, `$monitor`, and VHDL postponed processes.
- Add `StrobeBIOpConverion` in MooreTocore lowering.
- Add `sv.strobe` op to SV dialect, analogous to `sv.write` and wire it in SVVisitors.h and ExportVerilog to emit `$strove(...)`
- Extend `lowerPrintFormattedProcToSV`in SimToSV to detect `sim.proc.print` inside `sim.defer`, and emit `sv.strobe`.
- Add tests for each stage of the pipeline.
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circt-bot Bot commented May 28, 2026

Results of circt-tests run for ec313d3 compared to results for 3e54636:

sv-tests

Changes in emitted diagnostics:

  • -6 total change
  • -5 error: unsupported system call `$strobe`
  • -1 error: unsupported system call `$strobeb`

@fzi-hielscher
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fzi-hielscher commented May 28, 2026

Thanks @VecoMr. Unfortunately, I think the lowering of $stobe will be more complicated than that. Consider this example:

module strobeMod(input clk);
  logic [7:0] counter = '0;
  logic [7:0] counterInc;
  
  always @(posedge clk) begin
    counter <= counter + 1;
    counterInc = counter + 1;
    $strobe("%d - %d", counter + 1, counterInc);
  end
endmodule

In simulation this will produce

2 -   1
3 -   2
4 -   3
[...]

So, the increment that is happening within $strobe's argument list also has to be deferred. Frankly, I cannot tell you at the moment how we would do this. Maybe slang's AST gives us enough information so we can easily find out where we need to make the cut. But I could also imagine that there are more complex scenarios which might require us to feed this through LLHD first.

Update:
I noticed that my comment kind of misses the fundamental problem here: It is not so much about where the increment operation is happening, but where the probes of the signals are happening. The incremented value in counterInc probes counter in the active region, while the probe for the argument expression of $strobe has to occur in the postponed region.

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