[FIRRTL] EliminateWires: preserve sv.attributes when converting WireOp to NodeOp#10519
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[FIRRTL] EliminateWires: preserve sv.attributes when converting WireOp to NodeOp#10519bheneffe wants to merge 1 commit into
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seldridge
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LGTM. Only a few nits.
Thanks for fixing this. This would be surprising when it gets dropped!
…p to NodeOp When LowerAnnotations processes firrtl.AttributeAnnotation (the mechanism used by Chisel's addAttribute()), it sets sv.attributes on the FIRRTL WireOp. EliminateWires then converts single-writer passive WireOps to NodeOps without copying sv.attributes, causing attributes like mark_debug to be silently dropped before LowerToHW runs. Copy sv.attributes from the WireOp to the replacement NodeOp, matching the existing pattern in LowerToHW.cpp for RegOp and RegResetOp. Assisted-by: vscode/eicp:Claude Opus 4.6
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Hey @seldridge |
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Results of circt-tests run for 500a664 compared to results for 5306f6f: sv-testsChanges in emitted diagnostics:
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Hi,
I ran into this while trying to use Chisel's
addAttribute()to annotate a wire with(* mark_debug = "true" *)for Vivado debug probes. The attribute was set correctly byLowerAnnotations(assv.attributeson the FIRRTLWireOp), but never appeared in the emitted SystemVerilog.Root cause:
EliminateWiresconverts single-writer passiveWireOps toNodeOps without copyingsv.attributes, so they get silently dropped beforeLowerToHWruns.Proposed fix: copy
sv.attributesfrom theWireOpto the replacementNodeOp, matching the existing pattern inLowerToHW.cppforRegOpandRegResetOp.Assisted-by: vscode/eicp:Claude Opus 4.6