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Flexible Multiplexer Implementation using Altera Quartus, Python 3 and MyHDL

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MyHDL Python Demo Project

Demonstration of:

  • MyHDL Block Hierarchy using Demultiplexer and D-FlipFlop implementation
  • Testbench Test Trace viewable on GTKWave

Environment:

  • Python 3.9.4 64-bit
  • Visual Studio Code
  • Altera Quartus Prime 20.1.1 Lite Edition
  • myHDL 0.11
  • GTKWave for VCD wave viewing

Author: Jeff P

Image of Flexible Demux TestBench VCD Result

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Flexible Multiplexer Implementation using Altera Quartus, Python 3 and MyHDL

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