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[codex] fix simson Vendetta audio balance #1449

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[codex] fix simson Vendetta audio balance #1449

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6 changes: 2 additions & 4 deletions cores/simson/cfg/mem.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,14 +11,12 @@ clocks:
- cen_fm
- cen_fm2
audio:
gain: 0.97
rsum: 50k
channels:
# both FM and PCM are mixed inside K053260, then converted with the same YM3012 DAC
# the 0.033MM capacitor in sch. has a 333K mark (physical device). 33nF must be right
# but 985 Ohm and 33nF is just too heavy damping, especially for the FM part that does
# not need an antialising filter. So I am using a much lighter 1nF instead that will
# let users hear the FM music better
- { name: snd, module: jt053260, rsum: 50k, rc: [ { r: 1rout, c: 2.2n }, { r: 985, c: 1n } ]}
- { name: snd, module: jt053260, rsum: 50k, rc: [ { r: 1rout, c: 2.2n }, { r: 985, c: 33n } ]}
sdram:
banks:
- buses:
Expand Down
2 changes: 1 addition & 1 deletion cores/simson/hdl/jtsimson_sound.v
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Original file line number Diff line number Diff line change
Expand Up @@ -198,7 +198,7 @@ jt51 u_jt51(
.xright ( )
);
/* verilator tracing_off */
jt053260 u_pcm(
jt053260 #(.ADPCM_SAT(4'b0000),.AUX_MODE_EN(0)) u_pcm(
.rst ( rst_z80 ),
.clk ( clk ),
.cen ( cen_fm ),
Expand Down
12 changes: 6 additions & 6 deletions modules/jt053260/hdl/jt053260.v
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Expand Up @@ -16,7 +16,7 @@
Version: 1.0
Date: 14-4-2023 */

module jt053260(
module jt053260#(parameter [3:0] ADPCM_SAT=4'hF, parameter AUX_MODE_EN=1)(
input rst,
input clk,
input cen,
Expand Down Expand Up @@ -95,7 +95,7 @@ assign mmr_we = {4{ cs & ~wr_n & mmr_en }} &
assign tst_nx = tst_rd & ~tst_rdl;
assign left_en = sum_en[4:0];
assign right_en={sum_en[5],sum_en[3:0]};
assign aux_en = mode[3:2];
assign aux_en = AUX_MODE_EN ? mode[3:2] : 2'b11;
`ifdef SIMULATION
assign tim2_enb= test_2b[3]; // it should disable tim2 when high. Not connected for now
wire any_wr = cs & ~wr_n;
Expand Down Expand Up @@ -234,7 +234,7 @@ always @* begin
pan3_r = pan_dec_r( ch3_pan );
end

jt053260_channel #(.TESTRD(1)) u_ch0(
jt053260_channel #(.TESTRD(1),.ADPCM_SAT(ADPCM_SAT[0])) u_ch0(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
Expand Down Expand Up @@ -263,7 +263,7 @@ jt053260_channel #(.TESTRD(1)) u_ch0(
.snd_r ( ch0_snd_r )
);

jt053260_channel u_ch1(
jt053260_channel #(.ADPCM_SAT(ADPCM_SAT[1])) u_ch1(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
Expand Down Expand Up @@ -292,7 +292,7 @@ jt053260_channel u_ch1(
.snd_r ( ch1_snd_r )
);

jt053260_channel u_ch2(
jt053260_channel #(.ADPCM_SAT(ADPCM_SAT[2])) u_ch2(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
Expand Down Expand Up @@ -321,7 +321,7 @@ jt053260_channel u_ch2(
.snd_r ( ch2_snd_r )
);

jt053260_channel u_ch3(
jt053260_channel #(.ADPCM_SAT(ADPCM_SAT[3])) u_ch3(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
Expand Down
4 changes: 2 additions & 2 deletions modules/jt053260/hdl/jt053260_channel.v
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
Version: 1.0
Date: 14-4-2023 */

module jt053260_channel#(parameter TESTRD=0)(
module jt053260_channel#(parameter TESTRD=0, parameter ADPCM_SAT=1)(
input rst,
input clk,
input cen,
Expand Down Expand Up @@ -168,7 +168,7 @@ always @(posedge clk) begin
end
end
end
pre_snd <= adpcm_en ? adpcm_lim : rom_data;
pre_snd <= adpcm_en ? (ADPCM_SAT ? adpcm_lim : pre_snd + kadpcm) : rom_data;
end
end
end
Expand Down
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