LP & ULP cores - Fix C6 LP interrupt numbers, add GPIO_INT interrupt to ULP cores, collect S3-ULP pins into an array.

[leighleighleigh]

Happy to split this into multiple PRs if needed!

1. GPIO_INT was missing from these ULP cores, adding it will unblock this PR
2. Collect S3-ULP pins into an array, update S2-ULP pin method prefix, to make it easier to write GPIO APIs
3. The C6 interrupt numbers did not match the TRM
4. Added work-around for Peripheral struct generation for ULP/LP cores.

[leighleighleigh]

I just found out that the Peripherals API is generated from svd2rust - I'm not sure if I should be editing it manually...?

[burrbull]

1st issue you should open in svd2rust repo.

2nd issue you should fix in https://github.com/esp-rs/esp-pacs/blob/main/esp32s2-ulp%2Fsvd%2Fpatches%2Fesp32s2-ulp.yaml

[leighleighleigh]

Thanks @burrbull - these changes are now driven entirely by cargo xtask generate.
I have reverted item 1, and item 2 was addressed by adding the proper <interrupt> block to the relevant SVD files.

[leighleighleigh]

Regarding my issue with Peripherals::take().unwrap(), I figured out the cause. It was very obvious in hindsight!

Because I'm using the ULP Timer to run the code, the main() function has effectively become a giant loop {}.
Calling Peripherals::take().unwrap() inside of a loop is obviously going to panic... 🙃

Specifically, the panic occurs because the DEVICE_PERIPHERALS variable persists across calls to main() - due to the RTC_SLOW memory of the ULP code.

I'm not sure if this will require an esp-pacs change to address, I haven't thought about it yet.
I will address this in esp-lp-hal, and won't require a change to esp-pacs.