GPIO refactor

esp-hal/src/gpio/dedicated/low_level/esp32s2.rs

@@ -0,0 +1,31 @@
+#[inline(always)]
+pub(super) fn initialize() {
+    // Allow instruction access, which has better performance than register access.
+    let regs = unsafe { esp32s2::DEDICATED_GPIO::steal() };
+    regs.out_cpu()
+        .write(|w| unsafe { w.bits((1 << property!("dedicated_gpio.channel_count")) - 1) });
+}
+
+#[inline(always)]
+pub(super) fn set_output_enabled(_mask: u32, _en: bool) {
+    // Nothing to do.
+}
+
+#[inline(always)]
+pub(super) fn read_in() -> u32 {
+    let val;
+    unsafe { core::arch::asm!("get_gpio_in {0}", out(reg) val) };
+    val
+}
+
+#[inline(always)]
+pub(super) fn read_out() -> u32 {
+    let val;
+    unsafe { core::arch::asm!("rur.gpio_out {0}", out(reg) val) };
+    val
+}
+
+#[inline(always)]
+pub(super) fn write(mask: u32, value: u32) {
+    unsafe { core::arch::asm!("wr_mask_gpio_out {0}, {1}", in(reg) mask, in(reg) value) }
+}

esp-hal/src/gpio/dedicated/low_level/esp32s3.rs

@@ -0,0 +1,19 @@
+#[inline(always)]
+pub(super) fn initialize() {}
+
+#[inline(always)]
+pub(super) fn set_output_enabled(_mask: u32, _en: bool) {
+    // Nothing to do.
+}
+
+#[inline(always)]
+pub(super) fn read_in() -> u32 {
+    let val;
+    unsafe { core::arch::asm!("ee.get_gpio_in {0}", out(reg) val) };
+    val
+}
+
+#[inline(always)]
+pub(super) fn write(mask: u32, value: u32) {
+    unsafe { core::arch::asm!("ee.wr_mask_gpio_out {0}, {1}", in(reg) mask, in(reg) value) }
+}

esp-hal/src/gpio/dedicated/low_level/riscv_v1.rs

@@ -0,0 +1,40 @@
+// CSR_GPIO_OEN_USER   0x803
+// CSR_GPIO_IN_USER    0x804
+// CSR_GPIO_OUT_USER   0x805
+
+#[inline(always)]
+pub(super) fn set_output_enabled(mask: u32, en: bool) {
+    riscv::read_csr!(0x803);
+    riscv::write_csr!(0x803);
+
+    unsafe {
+        let bits = _read();
+        if en {
+            _write(bits | mask as usize)
+        } else {
+            _write(bits & !mask as usize)
+        }
+    }
+}
+
+#[inline(always)]
+pub(super) fn read_in() -> u32 {
+    riscv::read_csr!(0x804);
+    unsafe { _read() as u32 }
+}
+
+#[inline(always)]
+pub(super) fn read_out() -> u32 {
+    riscv::read_csr!(0x805);
+    unsafe { _read() as u32 }
+}
+
+#[inline(always)]
+pub(super) fn write(mask: u32, value: u32) {
+    riscv::set!(0x805);
+    riscv::clear!(0x805);
+    unsafe {
+        _set((mask & value) as usize);
+        _clear((mask & !value) as usize);
+    }
+}