Skip to content

stm32/sdmmc: impl. retry ocr and start_clocks #5890

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
xoviat merged 2 commits into from
Apr 18, 2026
Merged

stm32/sdmmc: impl. retry ocr and start_clocks #5890

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
2816d3c
stm32/sdmmc: impl. retry ocr
xoviat Apr 18, 2026
a525248
cyw: add more handling for cyw4373
xoviat Apr 18, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions cyw43/src/consts.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -207,6 +207,7 @@ pub(crate) const SDIOD_CCCR_BLKSIZE_0: u32 = 0x10;
pub(crate) const SDIOD_CCCR_SPEED_CONTROL: u32 = 0x13;
pub(crate) const SDIOD_CCCR_BRCM_CARDCAP: u32 = 0xf0;
pub(crate) const SDIOD_SEP_INT_CTL: u32 = 0xf2;
pub(crate) const SDIOD_CCCR_IOABORT: u32 = 0x06;
pub(crate) const SDIOD_CCCR_F1BLKSIZE_0: u32 = 0x110;
pub(crate) const SDIOD_CCCR_F2BLKSIZE_0: u32 = 0x210;
pub(crate) const SDIOD_CCCR_F2BLKSIZE_1: u32 = 0x211;
Expand All @@ -229,6 +230,8 @@ pub(crate) const SEP_INTR_CTL_POL: u32 = 0x04; // out-of-band interrupt polarity
pub(crate) const CHIPCOMMON_BASE_ADDRESS: u32 = 0x18000000;
pub(crate) const SDIO_BASE_ADDRESS: u32 = 0x18002000;

pub(crate) const SFC_RF_TERM: u8 = 1 << 0;

// Security type (authentication and encryption types are combined using bit mask)
#[allow(non_camel_case_types)]
#[derive(Copy, Clone, PartialEq)]
Expand Down
Loading