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[Scala3] Move BlackBoxSpec and ChiselStageSpec #5394

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Merged
adkian-sifive merged 4 commits into from
Jun 2, 2026
+19 −21
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[Scala3] Move BlackBoxSpec and ChiselStageSpec #5394

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3c2dab4
[Scala3] Move BlackBoxSpec and ChiselStageSpec
adkian-sifive May 28, 2026
0a24707
undo IO change
adkian-sifive May 29, 2026
27cad3c
undo selftype change
adkian-sifive May 29, 2026
ae9e6a8
Merge branch 'main' into adkian-sifive/scala3-blackboxspec
adkian-sifive May 29, 2026
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4 changes: 2 additions & 2 deletions src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ object TestHarnessWithMonitorSocket {
@instantiable
trait HasMonitorSocket { this: RawModule =>
protected def makeProbe(bundle: ProtocolBundle): ProtocolBundle = {
val monProbe = IO(probe.Probe(chiselTypeOf(bundle)))
val monProbe = chisel3.IO(probe.Probe(chiselTypeOf(bundle)))
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@jackkoenig jackkoenig May 29, 2026

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Can you explain why this is necessary?

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@adkian-sifive adkian-sifive May 29, 2026 •
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I've pulled this change into #5396, will comment there and undo this change

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@adkian-sifive adkian-sifive May 29, 2026

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But re other similar changes in this pr: Scala 3 cannot get access to IO with the selftype pattern

trait Something { this: RawModule => ...

and hits this error: illegal access to protected method IO in class BaseModule from trait Something

probe.define(monProbe, probe.ProbeValue(bundle))
monProbe
}
Expand Down Expand Up @@ -67,7 +67,7 @@ object ProtocolChecks {
}
}

trait HasTestsProperty { this: RawModule with HasTests =>
trait HasTestsProperty extends RawModule with HasTests {
def enableTestsProperty: Boolean

val testNames = Option.when(enableTestsProperty) {
Expand Down
2 changes: 1 addition & 1 deletion src/test/scala-2/chiselTests/BlackBox.scala → src/test/scala/chiselTests/BlackBox.scala
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Expand Up @@ -374,7 +374,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe
object A extends layer.Layer(layer.LayerConfig.Extract())

sealed trait NoIo { this: BlackBox @nowarn("cat=deprecation") =>
final val io = IO(new Bundle {})
final val io = chisel3.IO(new Bundle {})
}

// No known layers
Expand Down
38 changes: 18 additions & 20 deletions ...-2/circtTests/stage/ChiselStageSpec.scala → ...la/circtTests/stage/ChiselStageSpec.scala
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Expand Up @@ -10,7 +10,7 @@ import chisel3.testing.scalatest.FileCheck
import circt.stage.{ChiselStage, FirtoolOption, PreserveAggregate}

import _root_.logger.LogLevel
import firrtl.EmittedVerilogCircuitAnnotation
import firrtl.{annoSeqToSeq, seqToAnnoSeq, EmittedVerilogCircuitAnnotation}
import firrtl.stage.FirrtlCircuitAnnotation

import java.io.File
Expand Down Expand Up @@ -123,12 +123,12 @@ object ChiselStageSpec {
}

class RecoverableErrorFakeSourceInfo extends RawModule {
implicit val info = SourceLine("Foo", 3, 10)
implicit val info: SourceLine = SourceLine("Foo", 3, 10)
3.U >> -1
}

class ErrorCaughtByFirtool extends RawModule {
implicit val info = SourceLine("Foo", 3, 10)
implicit val info: SourceLine = SourceLine("Foo", 3, 10)
val w = Wire(UInt(8.W))
}

Expand Down Expand Up @@ -552,7 +552,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
message should include("Something bad happened")

info("The exception should not contain a stack trace")
exception.getStackTrace should be(Array())
exception.getStackTrace should be(Array.empty[StackTraceElement])
}

it("should NOT include a stack trace for recoverable errors") {
Expand All @@ -569,7 +569,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
message should include("Fatal errors during hardware elaboration. Look above for error list.")

info("The exception should not contain a stack trace")
exception.getStackTrace should be(Array())
exception.getStackTrace should be(Array.empty[StackTraceElement])
}

it("should include a stack trace for recoverable errors with '--throw-on-first-error'") {
Expand Down Expand Up @@ -617,9 +617,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils

val lines = stdout.split("\n")
// Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
lines(0) should include(
"src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 122:9: Negative shift amounts are illegal (got -1)"
)
lines(0) should include("src/test/scala/circtTests/stage/ChiselStageSpec.scala 122:")
lines(0) should include(": Negative shift amounts are illegal (got -1)")
lines(1) should include(" 3.U >> -1")
lines(2) should include(" ^")
}
Expand All @@ -638,9 +637,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
val lines = stdout.split("\n")
// Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match
lines.size should equal(2)
lines(0) should include(
"src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 122:9: Negative shift amounts are illegal (got -1)"
)
lines(0) should include("src/test/scala/circtTests/stage/ChiselStageSpec.scala 122:")
lines(0) should include(": Negative shift amounts are illegal (got -1)")
(lines(1) should not).include("3.U >> -1")
}

Expand Down Expand Up @@ -743,8 +741,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
import chisel3.util.experimental.InlineInstance

trait SimpleIO { this: RawModule =>
val a = IO(Input(Bool()))
val b = IO(Output(Bool()))
val a = chisel3.IO(Input(Bool()))
val b = chisel3.IO(Output(Bool()))
}

class Bar extends RawModule with SimpleIO with InlineInstance {
Expand Down Expand Up @@ -781,8 +779,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
import chisel3.util.experimental.FlattenInstance

trait SimpleIO { this: RawModule =>
val a = IO(Input(Bool()))
val b = IO(Output(Bool()))
val a = chisel3.IO(Input(Bool()))
val b = chisel3.IO(Output(Bool()))
}

class Baz extends RawModule with SimpleIO {
Expand Down Expand Up @@ -941,8 +939,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
import chisel3.util.experimental.{forceName, InlineInstance}

trait SimpleIO { this: RawModule =>
val a = IO(Input(Bool()))
val b = IO(Output(Bool()))
val a = chisel3.IO(Input(Bool()))
val b = chisel3.IO(Output(Bool()))
}

class Baz extends RawModule with SimpleIO {
Expand Down Expand Up @@ -1388,7 +1386,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
message should include("Something bad happened")

info("The exception should not contain a stack trace")
exception.getStackTrace should be(Array())
exception.getStackTrace should be(Array.empty[StackTraceElement])
}

it("should NOT include a stack trace for recoverable errors") {
Expand All @@ -1401,7 +1399,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
message should include("Fatal errors during hardware elaboration. Look above for error list.")

info("The exception should not contain a stack trace")
exception.getStackTrace should be(Array())
exception.getStackTrace should be(Array.empty[StackTraceElement])
}

it("should report a specific error if firtool is not found on the PATH") {
Expand All @@ -1415,7 +1413,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils
message should include("Chisel requires firtool, the MLIR-based FIRRTL Compiler (MFC), to generate Verilog.")

info("The exception should not contain a stack trace")
exception.getStackTrace should be(Array())
exception.getStackTrace should be(Array.empty[StackTraceElement])
}

}
Expand Down
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