hw/mcu: STM32H7 Add dcache support

[kasjer]

Device supports DCache now it's enabled by default.

Enabling DCACHE may increase performance quite a lot

Coremark run without cache (before patch applied)

Coremark running on weact_h743vi at 480 MHz

2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 2164
Total time (secs): 16
Iterations/Sec   : 687
Iterations       : 11000
Compiler version : GCC13.3.0
Compiler flags   :
Memory location  : STACK
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x33ff
Correct operation validated. See readme.txt for run and reporting rules.

With cache enabled iteration per second increased from 687 to 2000

Coremark running on weact_h743vi at 480 MHz

2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 1960
Total time (secs): 15
Iterations/Sec   : 2000
Iterations       : 30000
Compiler version : GCC13.3.0
Compiler flags   :
Memory location  : STACK
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x5275
Correct operation validated. See readme.txt for run and reporting rules.