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Fixed some parameter and ref placement #4

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Fixed some parameter and ref placement #4

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2 changes: 1 addition & 1 deletion fpga/common/rtl/mqnic_interface_rx.v
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Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ module mqnic_interface_rx #
parameter DMA_ADDR_WIDTH = 64,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH,
parameter RAM_ADDR_WIDTH = $clog2(RX_RAM_SIZE),
parameter RAM_SEG_COUNT = 2,
parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
Expand Down Expand Up @@ -222,7 +223,6 @@ module mqnic_interface_rx #
);

parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;

parameter REQ_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);

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2 changes: 1 addition & 1 deletion fpga/common/rtl/mqnic_interface_tx.v
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Expand Up @@ -53,6 +53,7 @@ module mqnic_interface_tx #
parameter DMA_ADDR_WIDTH = 64,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE),
parameter RAM_SEG_COUNT = 2,
parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT,
Expand Down Expand Up @@ -208,7 +209,6 @@ module mqnic_interface_tx #
);

parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE);
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;

wire [AXIS_DESC_DATA_WIDTH-1:0] tx_fifo_desc_tdata;
wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_fifo_desc_tkeep;
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9 changes: 9 additions & 0 deletions fpga/common/tb/cmac_pad/sim_build/test_cmac_pad/ax6me1mp_results.xml
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<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1755064541" />
<testcase name="run_test_001" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.22164702415466309" sim_time_ns="800.001" ratio_time="3609.3469021346627" />
<testcase name="run_test_002" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.255415678024292" sim_time_ns="3104.001" ratio_time="12152.742635104749" />
<testcase name="run_test_pad_001" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.06339192390441895" sim_time_ns="272.00099999999975" ratio_time="4290.783166797672" />
<testcase name="run_test_pad_002" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.07956147193908691" sim_time_ns="976.0010000000002" ratio_time="12267.256703687392" />
</testsuite>
</testsuites>
9 changes: 9 additions & 0 deletions fpga/common/tb/cmac_pad/sim_build/test_cmac_pad/q285ux5n_results.xml
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<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1755064953" />
<testcase name="run_test_001" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.6149158477783203" sim_time_ns="800.001" ratio_time="1300.9926527188866" />
<testcase name="run_test_002" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.6838090419769287" sim_time_ns="3104.001" ratio_time="4539.280426924696" />
<testcase name="run_test_pad_001" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.15745258331298828" sim_time_ns="272.00099999999975" ratio_time="1727.510557634416" />
<testcase name="run_test_pad_002" classname="test_cmac_pad" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.22379493713378906" sim_time_ns="976.0010000000002" ratio_time="4361.139767056157" />
</testsuite>
</testsuites>
6 changes: 6 additions & 0 deletions fpga/common/tb/cpl_queue_manager/sim_build/test_cpl_queue_manager/h1dmhgdz_results.xml
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<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1755064542" />
<testcase name="run_test_001" classname="test_cpl_queue_manager" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="0.5671844482421875" sim_time_ns="9972.001" ratio_time="17581.583964273224" />
</testsuite>
</testsuites>
6 changes: 6 additions & 0 deletions fpga/common/tb/cpl_queue_manager/sim_build/test_cpl_queue_manager/zp5g120k_results.xml
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<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1755064956" />
<testcase name="run_test_001" classname="test_cpl_queue_manager" file="/home/szb/DV/corundum/.tox/py3/lib/python3.12/site-packages/cocotb/regression.py" lineno="713" time="3.9866089820861816" sim_time_ns="9972.001" ratio_time="2501.37423680355" />
</testsuite>
</testsuites>
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6 changes: 3 additions & 3 deletions fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
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Expand Up @@ -425,6 +425,9 @@ wire sfp_i2c_select_scl_o;
wire sfp_i2c_select_sda_o;
wire [7:0] sfp_i2c_select;

reg sfp_i2c_scl_o_reg = 1'b1;
reg sfp_i2c_sda_o_reg = 1'b1;

wire sfp_i2c_scl_i_int = sfp_i2c_scl_i & sfp_i2c_scl_o;
wire sfp_i2c_sda_i_int = (sfp_1_i2c_sda_i || !sfp_i2c_select[0]) && (sfp_2_i2c_sda_i || !sfp_i2c_select[1]) & sfp_i2c_sda_o_reg & sfp_i2c_select_sda_o;

Expand All @@ -433,9 +436,6 @@ reg sfp_1_rs_reg = 1'b0;
reg sfp_2_tx_disable_reg = 1'b0;
reg sfp_2_rs_reg = 1'b0;

reg sfp_i2c_scl_o_reg = 1'b1;
reg sfp_i2c_sda_o_reg = 1'b1;

reg eeprom_i2c_scl_o_reg = 1'b1;
reg eeprom_i2c_sda_o_reg = 1'b1;

Expand Down