v1.2.0

.github/workflows/Pipeline.yml

@@ -7,7 +7,18 @@ on:
   schedule:
     - cron: '0 15 * * *'
 
+permissions:
+  contents: read
+  pages:    write
+  id-token: write
+
 jobs:
+  Prepare:
+    uses: pyTooling/Actions/.github/workflows/PrepareJob.yml@r7
+    with:
+      main_branch:    'main'
+      release_branch: 'main'
+
   NVC:
     name: ${{ matrix.icon }}${{ matrix.name }} - NVC
     runs-on: ${{ matrix.image }}
@@ -16,16 +27,16 @@ jobs:
       matrix:
         include:
           - {icon: "🐧",   name: "Ubuntu",  image: "ubuntu-24.04", shell: "bash"}
-##        - {icon: "🪟",   name: "Windows", image: "windows-2022", shell: "powershell"}      # Scripting is Bash-based
-          - {icon: "🪟🟨", name: "Windows", image: "windows-2022", shell: "msys2 {0}"}       # Installation in Windows via MSI, but called from UCRT64.
+##        - {icon: "🪟",   name: "Windows", image: "windows-2025", shell: "powershell"}      # Scripting is Bash-based
+          - {icon: "🪟🟨", name: "Windows", image: "windows-2025", shell: "msys2 {0}"}       # Installation in Windows via MSI, but called from UCRT64.
 
     defaults:
       run:
         shell: ${{ matrix.shell }}
 
     steps:
       - name: ⏬ Checkout repository
-        uses: actions/checkout@v4
+        uses: actions/checkout@v6
         with:
           submodules: recursive
 
@@ -60,27 +71,106 @@ jobs:
           ../scripts/NVC.sh
 
       - name: 🚧 Inspect Ant+JUnit Unittest Summary XML
-#        if: matrix.name == 'Ubuntu'
         run: |
           cat temp/*.xml
 
       - name: '📤 Upload artifact: logs'
-        uses: actions/upload-artifact@v4
+        uses: pyTooling/upload-artifact@v7
         with:
-          name: junit-${{ matrix.name }}-nvc
+          name: Interfaces-NVC-XML-${{ matrix.name }}
           include-hidden-files: true
           path: |
             temp/*.xml
           if-no-files-found: error
           retention-days: 1
 
   PublishTestResults:
-    uses: pyTooling/Actions/.github/workflows/PublishTestResults.yml@r5
+    uses: pyTooling/Actions/.github/workflows/PublishTestResults.yml@r7
     needs:
       - NVC
     with:
-      unittest_artifacts_pattern: "junit-*"
+      unittest_artifacts_pattern: "Interfaces-NVC-XML-*"
       testsuite-summary-name:     "Interfaces"
+      additional_merge_args:      '"--pytest=reduce-depth:Interfaces" --render=tree'
+      merged_junit_artifact:      'Interfaces-Report-XML'
       dorny:                      true
 #      codecov:                    true
+#    secrets:
+#      CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}
+
+  IntermediateCleanUp:
+    uses: pyTooling/Actions/.github/workflows/CleanupArtifacts.yml@r7
+    needs:
+      - PublishTestResults
+    with:
+      others: |
+        Interfaces-NVC-XML-*
+
+  Documentation:
+    uses: pyTooling/Actions/.github/workflows/SphinxDocumentation.yml@r7
+    needs:
+      - PublishTestResults
+#    if: success() || failure()
+    with:
+      requirements:          '-r doc/requirements.txt'
+      doc_directory:         'doc'
+      unittest_xml_artifact: 'Interfaces-Report-XML'
+      html_artifact:         'Interfaces-HTML'
+      latex_artifact:        'Interfaces-LaTeX'
+
+  PDFDocumentation:
+    uses: pyTooling/Actions/.github/workflows/LaTeXDocumentation.yml@r7
+    needs:
+      - Documentation
+    if: (success() || failure()) && needs.Documentation.result == 'success'
+    with:
+      document:       'Interfaces'
+      latex_artifact: 'Interfaces-LaTeX'
+      miktex_image:   'pytooling/miktex:sphinx'
+      pdf_artifact:   'Interfaces-PDF'
+      can-fail:       'true'
+
+  PublishToGitHubPages:
+    uses: pyTooling/Actions/.github/workflows/PublishToGitHubPages.yml@r7
+    needs:
+      - NVC
+      - Documentation
+#    if: (success() || failure()) && needs.Documentation.result == 'success'
+    with:
+      doc:      'Interfaces-HTML'
+#      coverage: 'Interfaces-Coverage-HTML'
+
+  AutoTag:
+    uses: pyTooling/Actions/.github/workflows/TagReleaseCommit.yml@r7
+    needs:
+      - Prepare
+      - PublishToGitHubPages
+    if: needs.Prepare.outputs.is_release_commit == 'true' && github.event_name != 'schedule'
+    permissions:
+      contents: write  # required for create tag
+      actions:  write  # required for trigger workflow
+    with:
+      version:  ${{ needs.Prepare.outputs.version }}
+      auto_tag: ${{ needs.Prepare.outputs.is_release_commit }}
+
+  Release:
+    uses: pyTooling/Actions/.github/workflows/PublishReleaseNotes.yml@r7
+    needs:
+      - Prepare
+      - PublishToGitHubPages
+    if: needs.Prepare.outputs.is_release_tag == 'true'
+    permissions:
+      contents: write
+      actions:  write
+    with:
+      prerelease: true
+      replacements: |
+        version=${{ needs.Prepare.outputs.version }}
+      tag: ${{ needs.Prepare.outputs.version }}
+      description: |
+        # Interfaces %version%
+      inventory-json: "inventory.json"
+      inventory-version: ${{ needs.Prepare.outputs.version }}
+      assets: |
+
     secrets: inherit

AMBA/AXI/v4/AXI4.vhdl

@@ -11,7 +11,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -176,5 +176,4 @@ package Axi4 is
 		ReadData       : view Axi4_ReadData_ManagerView;
 	end view;
 	alias Axi4_SubordinateView is Axi4_ManagerView'converse;
-
 end package;

AMBA/AXI/v4/AXI4Common.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -88,5 +88,4 @@ package Axi4Common is
 		Clock  : std_ulogic;
 		Reset  : std_ulogic;
 	end record;
-
 end package;

AMBA/AXI/v4/AXI4Lite.presized.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.

AMBA/AXI/v4/AXI4Lite.vhdl

@@ -11,7 +11,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.

AMBA/AXI/v4/AXI4Lite_Generic.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.

AMBA/AXI/v4/AXI4Stream.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.

AMBA/AXI/v4/AXI4Stream_Generic.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -41,5 +41,4 @@ package Axi4Stream_Generic is
 		Keep(KEEP_BITS - 1 downto 0),
 		User(USER_BITS -  1 downto 0)
 	);
-
 end package;

AMBA/AXI/v4/AXI4_Generic.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2016-2025 Open Source VHDL Group
+-- Copyright 2016-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.

Avalon/v1/AvalonCommon.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2025-2025 Open Source VHDL Group
+-- Copyright 2025-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -32,9 +32,9 @@ use     IEEE.numeric_std.all;
 package AvalonCommon is
 	-- Common types
 	subtype Data_Type        is std_ulogic_vector;
-	subtype Address_Type     is unsigned;
+	subtype Address_Type     is unresolved_unsigned;
 	subtype ByteEnable_Type  is std_ulogic_vector;
-	subtype BurstCount_Type  is unsigned;
+	subtype BurstCount_Type  is unresolved_unsigned;
 
 	-- Avalon-MM Response
 	subtype Response_Type is std_ulogic_vector(1 downto 0);
@@ -47,5 +47,4 @@ package AvalonCommon is
 		Clock  : std_ulogic;
 		Reset  : std_ulogic;
 	end record;
-
 end package;

Avalon/v1/AvalonMM.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2025-2025 Open Source VHDL Group
+-- Copyright 2025-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -40,22 +40,22 @@ package AvalonMM is
 		Write              : std_ulogic;        -- Write request
 		WriteData          : Data_Type;         -- Write data
 		ByteEnable         : ByteEnable_Type;   -- Byte enable
-		
+
 		-- Slave signals
 		ReadData           : Data_Type;         -- Read data
 		ReadDataValid      : std_ulogic;        -- Read data valid
 		WaitRequest        : std_ulogic;        -- Wait request
 		Response           : Response_Type;     -- Response
-		
+
 		-- Optional burst signals
 		BurstCount         : BurstCount_Type;   -- Burst count
-		
+
 		-- Optional pipelining signals
 		WriteResponseValid : std_ulogic;        -- Write response valid
-		
+
 		-- Optional lock signal
 		Lock               : std_ulogic;        -- Lock
-		
+
 		-- Optional debug signals
 		DebugAccess        : std_ulogic;        -- Debug access
 	end record;
@@ -72,7 +72,7 @@ package AvalonMM is
 		BurstCount         : out;
 		Lock               : out;
 		DebugAccess        : out;
-		
+
 		-- Master inputs
 		ReadData           : in;
 		ReadDataValid      : in;
@@ -81,5 +81,4 @@ package AvalonMM is
 		WriteResponseValid : in;
 	end view;
 	alias AvalonMM_SlaveView is AvalonMM_MasterView'converse;
-
 end package;

Avalon/v1/AvalonMM_Generic.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2025-2025 Open Source VHDL Group
+-- Copyright 2025-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -52,5 +52,4 @@ package AvalonMM_Generic is
 		ByteEnable(BYTEENABLE_BITS - 1 downto 0),
 		BurstCount(BURSTCOUNT_BITS - 1 downto 0)
 	);
-
 end package;

Avalon/v1/AvalonMM_Minimal.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2025-2025 Open Source VHDL Group
+-- Copyright 2025-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -40,7 +40,7 @@ package AvalonMM_Minimal is
 		Write       : std_ulogic;
 		WriteData   : Data_Type;
 		ByteEnable  : ByteEnable_Type;
-		
+
 		-- Slave signals
 		ReadData    : Data_Type;
 		WaitRequest : std_ulogic;
@@ -55,11 +55,10 @@ package AvalonMM_Minimal is
 		Write       : out;
 		WriteData   : out;
 		ByteEnable  : out;
-		
+
 		-- Master inputs (slave outputs)
 		ReadData    : in;
 		WaitRequest : in;
 	end view;
 	alias AvalonMM_Minimal_SlaveView is AvalonMM_Minimal_MasterView'converse;
-
 end package;

Avalon/v1/AvalonMM_Minimal_Generic.vhdl

@@ -10,7 +10,7 @@
 --
 -- License:
 -- =============================================================================
--- Copyright 2025-2025 Open Source VHDL Group
+-- Copyright 2025-2026 Open Source VHDL Group
 --
 -- Licensed under the Apache License, Version 2.0 (the "License");
 -- you may not use this file except in compliance with the License.
@@ -49,5 +49,4 @@ package AvalonMM_Minimal_Generic is
 		ReadData(DATA_BITS - 1 downto 0),
 		ByteEnable(BYTEENABLE_BITS - 1 downto 0)
 	);
-
 end package;