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Spinball & Sleic support - #44
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… first 32 rows after an RDATA edge trigger
PastorL69
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gerwout
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May 27, 2026
Add a new doc dmd_wire_protocol.md that describes the serial signal protocol on the 14-pin ribbon between the PIC 16C54HS at IC23 and the gas plasma panel. Sources: - Saleae Logic 2 capture in PPUC/dmdreader (Io Moon - Sleic 128x32.sal) -- 6 channels at 12 MHz, ~44.5 s. - The PIO-based Sleic decoder added in PPUC/dmdreader#44 (May 2026). Concrete measurements now on file: - DOTCLK ~599 kHz, RCLK ~4.7 kHz, RDATA refresh ~145 Hz. - 8192 dot clocks per frame = 2 bitplanes x 128 x 32 pixels each. - Visible refresh ~72 fps (2 bitplanes summed per visible frame). - Frame boundary marker: DE LOW for >=100 us followed by RDATA HIGH. Also flagged a plane-order disagreement: the wire-side decoder (dmdreader) treats plane 0 as MSB (weight x2), while the ROM-side analysis in dmd_graphics.md treats plane 0 as LSB. Both are noted as candidates pending verification against a real panel; added a warning to dmd_graphics.md cross-linking dmd_wire_protocol.md. This wire protocol is not what a PinMAME driver needs to model -- the driver stops at the 80188-side DMD register window at A000h -- but it gives us: - An accurate refresh rate for the VSYNC IRQ (~72 Hz visible, not the 120/244 Hz the current PinMAME stub uses). - A way to validate decoded frames against ground truth from the panel. - A path to resolve the plane-order question. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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