Skip to content

docs: clarify RISC-V RVV target selection and GCC 14+ requirement for ZVL128B/ZVL256B #5819

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
trg-rgb wants to merge 1 commit into
base: develop
Choose a base branch
from
+51 −0

docs: clarify RISC-V RVV target selection and GCC 14+ requirement for…

601ff0e
Select commit
Loading
Failed to load commit list.
Open

docs: clarify RISC-V RVV target selection and GCC 14+ requirement for ZVL128B/ZVL256B #5819

docs: clarify RISC-V RVV target selection and GCC 14+ requirement for…
601ff0e
Select commit
Loading
Failed to load commit list.
Azure Pipelines / OpenMathLib.OpenBLAS (OSX_NDK_ARMV7) succeeded May 25, 2026 in 5m 16s

OSX_NDK_ARMV7 succeeded

0 errors / 0 warnings

View more details on Azure Pipelines