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.github/workflows/test.yml

@@ -0,0 +1,19 @@
+name: Test
+on:
+  push:
+  pull_request: 
+    branches: [main]
+
+jobs:
+  ci:
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout Repository
+        uses: actions/checkout@v3 # required
+      - name: Run Regression Tests
+        uses: Purdue-SoCET/SoCET-CI@main # core usage
+        with:
+          targets: | # List all FuseSoC Test Targets
+            make config
+            make verilate

.gitignore

@@ -1,12 +1,16 @@
 # ignore the build and run files
 build/
 sim_out/
+obj_dir/
+rvb_out/
 # ignore memory files from test cases
 *.hex
 meminit.ver
 verification/asm-tests/RV32I/*.elf
 verification/asm-tests/RV32I/*.log
 verification/asm-tests/RV32I/*.hex
+*.bin
+*.elf
 # config files are auto-generated
 source_code/include/component_selection_defines.vh
 verification/c-firmware/custom_instruction_calls.h
@@ -27,3 +31,62 @@ source_code/fpga/output_files
 *.lock-waf*
 # Ignore files for commands for moving stuff around
 *.cmd
+mitll*
+# Ignore temporary files created by gedit
+*~
+# Ignore test cache files
+run_tests_cache.json
+# Ignore log files and Verilator outputs
+*.log
+*.fst
+memsim.dump
+meminit.bin
+
+# ignore files auto-generated by vscode.
+_info
+_vmake
+*.qdb
+*.qtl
+*.qpg
+
+# ignore python bytecode files
+*.pyc
+__pycache__/
+
+# ignore xrun files
+INCA_libs/
+xcelium.d/
+xrun.history
+xrun.key
+.simvision
+waves.shm/
+
+open_files.sh
+
+# fusesoc
+fusesoc_libraries
+fusesoc.conf
+
+# synthesis scripts
+desflow1/
+.vscode/
+
+# uvm
+work
+mapped
+fpga
+transcript
+*.wlf
+README
+*.swp
+._*
+*.log
+*.deps
+*.hex
+*.ver
+mti*
+*.diff
+system.summary
+system_fpga.summary
+*.vstf
+*vsim*

.rules.verible_lint

@@ -0,0 +1,3 @@
+parameter-name-style=localparam_style:CamelCase|ALL_CAPS
+-explicit-function-lifetime
+-explicit-task-lifetime

Makefile

@@ -0,0 +1,88 @@
+ROOT := $(shell pwd)
+
+RISCV := $(ROOT)/source_code
+RISCV_CORE := $(RISCV)/standard_core
+PIPELINE := $(RISCV)/pipelines
+RISCV_PKGS := $(RISCV)/packages
+RISC_MGMT := $(RISCV)/risc_mgmt
+SPARCE := $(RISCV)/sparce
+PRIVS := $(RISCV)/privs
+BRANCH_PREDICT := $(RISCV)/branch_predictors
+CACHES := $(RISCV)/caches
+RISCV_BUS := $(RISCV)/bus_bridges
+RV32C := $(RISCV)/rv32c
+RV32M_FILES := $(RISC_MGMT)/extensions/rv32m/carry_save_adder.sv $(RISC_MGMT)/extensions/rv32m/flex_counter_mul.sv $(RISC_MGMT)/extensions/rv32m/full_adder.sv $(RISC_MGMT)/extensions/rv32m/pp_mul32.sv $(RISC_MGMT)/extensions/rv32m/radix4_divider.sv $(RISC_MGMT)/extensions/rv32m/rv32m_decode.sv $(RISC_MGMT)/extensions/rv32m/rv32m_execute.sv $(RISC_MGMT)/extensions/rv32m/rv32m_memory.sv
+RV32C_FILES := $(RV32C)/decompressor.sv $(RV32C)/fetch_buffer.sv $(RV32C)/rv32c_disabled.sv $(RV32C)/rv32c_enabled.sv $(RV32C)/rv32c_wrapper.sv
+RISC_MGMT_FILES := $(RISC_MGMT)/risc_mgmt_wrapper.sv $(RISC_MGMT)/tspp/tspp_risc_mgmt.sv $(RV32M_FILES)
+RISC_EXT_FILES := $(RISC_MGMT)/extensions/template/template_decode.sv $(RISC_MGMT)/extensions/template/template_execute.sv $(RISC_MGMT)/extensions/template/template_memory.sv
+CORE_PKG_FILES := $(RISCV_PKGS)/rv32i_types_pkg.sv $(RISCV_PKGS)/alu_types_pkg.sv $(RISCV_PKGS)/risc_mgmt/template_pkg.sv $(RISCV_PKGS)/risc_mgmt/crc32_pkg.sv $(RISCV_PKGS)/risc_mgmt/rv32m_pkg.sv $(RISCV_PKGS)/risc_mgmt/test_pkg.sv $(RISCV_PKGS)/machine_mode_types_pkg.sv $(RISCV_PKGS)/machine_mode_types_1_12_pkg.sv $(RISCV_PKGS)/pma_types_1_12_pkg.sv
+CORE_FILES := $(RISCV_CORE)/alu.sv  $(RISCV_CORE)/branch_res.sv  $(RISCV_CORE)/control_unit.sv  $(RISCV_CORE)/dmem_extender.sv  $(RISCV_CORE)/endian_swapper.sv  $(RISCV_CORE)/jump_calc.sv  $(RISCV_CORE)/memory_controller.sv  $(RISCV_CORE)/RISCVBusiness.sv  $(RISCV_CORE)/rv32i_reg_file.sv $(RISCV_CORE)/top_core.sv
+PIPELINE_FILES :=  $(PIPELINE)/tspp/tspp_execute_stage.sv  $(PIPELINE)/tspp/tspp_fetch_stage.sv  $(PIPELINE)/tspp/tspp_hazard_unit.sv  #$(PIPELINE)/tspp/tspp.sv
+PREDICTOR_FILES := $(BRANCH_PREDICT)/branch_predictor_wrapper.sv $(BRANCH_PREDICT)/nottaken_predictor/nottaken_predictor.sv
+PRIV_FILES := $(PRIVS)/priv_wrapper.sv  $(PRIVS)/priv_1_12/priv_1_12_block.sv  $(PRIVS)/priv_1_12/priv_1_12_int_ex_handler.sv  $(PRIVS)/priv_1_12/priv_1_12_csr.sv  $(PRIVS)/priv_1_12/priv_1_12_pipe_control.sv $(PRIVS)/priv_1_12/priv_1_12_pma.sv
+CACHE_FILES := $(CACHES)/caches_wrapper.sv $(CACHES)/pass_through/pass_through_cache.sv $(CACHES)/direct_mapped_tpf/direct_mapped_tpf_cache.sv $(CACHES)/separate_caches.sv
+SPARCE_FILES := $(SPARCE)/sparce_wrapper.sv $(SPARCE)/sparce_disabled/sparce_disabled.sv $(SPARCE)/sparce_enabled/sparce_cfid.sv  $(SPARCE)/sparce_enabled/sparce_enabled.sv  $(SPARCE)/sparce_enabled/sparce_psru.sv  $(SPARCE)/sparce_enabled/sparce_sasa_table.sv  $(SPARCE)/sparce_enabled/sparce_sprf.sv  $(SPARCE)/sparce_enabled/sparce_svc.sv
+RISCV_BUS_FILES := $(RISCV_BUS)/generic_nonpipeline.sv $(RISCV_BUS)/ahb.sv
+TRACKER_FILES := $(RISCV)/trackers/cpu_tracker.sv $(RISCV)/trackers/branch_tracker.sv
+
+COMPONENT_FILES_SV := $(CORE_PKG_FILES) $(RISC_MGMT_FILES) $(RISC_EXT_FILES) $(CORE_FILES) $(RV32C_FILES) $(PIPELINE_FILES) $(SPARCE_FILES) $(PREDICTOR_FILES) $(PRIV_FILES) $(CACHE_FILES) $(RISCV_BUS_FILES) $(TRACKER_FILES)
+
+TOP_ENTITY := RISCVBusiness
+
+HEADER_FILES := -I$(RISCV)/include
+
+
+define USAGE
+@echo "----------------------------------------------------------------------"
+@echo " Build Targets:"
+@echo "     config: config core with example.yml"
+@echo "     verilate: Invoke 'FuseSoC run --build' to build Verilator target"
+@echo "     xcelium: Invoke 'FuseSoC run --build' to build Xcelium target"
+@echo "     lint: Invoke 'FuseSoC run --build' to run the Verilator lint target"
+@echo "     clean: Remove build directories"
+@echo "     veryclean: Remove fusesoc libraries & build directories"
+@echo "----------------------------------------------------------------------"
+endef
+
+.phony: default clean config verilate xcelium
+
+
+default:
+	$(USAGE)
+
+config:
+	@echo "----------------------"
+	@echo " Running config_core"
+	@echo "----------------------"
+	@python3 scripts/config_core.py example.yml
+
+verilate: config
+	@fusesoc --cores-root . run --setup --build --build-root rvb_out --target sim --tool verilator socet:riscv:RISCVBusiness --make_options='-j'
+	@echo "------------------------------------------------------------------"
+	@echo "Build finished, you can run with 'fusesoc run', or by navigating"
+	@echo "to the build directory created by FuseSoC and using the Makefile there."
+	@echo "------------------------------------------------------------------"
+
+no_mem: config
+	@fusesoc --cores-root . run --setup --build --build-root rvb_out --target no_mc --tool verilator socet:riscv:RISCVBusiness --make_options='-j'
+	@echo "------------------------------------------------------------------"
+	@echo "Build finished, you can run with 'fusesoc run', or by navigating"
+	@echo "to the build directory created by FuseSoC and using the Makefile there."
+	@echo "------------------------------------------------------------------"
+
+xcelium: config
+	@fusesoc --cores-root . run --setup --build --build-root rvb_out --target sim --tool xcelium socet:riscv:RISCVBusiness
+	@echo "Build finished, you can run with 'fusesoc run', or by navigating"
+	@echo "to the build directory created by FuseSoC and using the Makefile there."
+
+lint: config
+	@fusesoc --cores-root . run --setup --build --build-root rvb_out --target lint --tool verilator socet:riscv:RISCVBusiness
+	@echo "Lint finished, no errors found"
+
+clean:
+	rm -rf build
+	rm -rf rvb_out
+
+veryclean:
+	rm -rf fusesoc_libraries
+	rm fusesoc.conf

README.md

@@ -4,12 +4,43 @@ Design documents and project information for the RISC-V Business project can be
 [RISCV-Business Documentation](https://wiki.itap.purdue.edu/display/RISC/RISCV-Business)
 
 **Current User-Level ISA Spec :** v2.1
-**Current Privileged ISA Spec :** v1.11
+**Current Privileged ISA Spec :** v1.12
 
 # Getting Started
 
 Getting started with RISCV Business consists of three steps: setting up the RISCV tool-chain, setting up the WAF build system, and finally interacting with the RISCV Business project itself. 
 
+## Fusesoc
+This project uses the [Fusesoc](http://fusesoc.net/) build system.  Use the following commands to get started...
+
+```bash
+# install project dependencies &
+# setup git pre-commit hook
+./setup.sh
+
+# For ease of use, use the makefile to run FuseSoC tests
+make # shows all build targets available
+
+# configure the RISC-V core
+make config 
+# or python3 scripts/config_core.py <custom>.yml
+#   if you want to use a config other than example.yml
+
+make verilate # build with Verilator, or...
+make xcelium # build with Xcelium
+```
+
+> Congrats! All dependencies are now set up.  Now you can run simulations/tests:
+
+
+```bash
+# Run ISA tests
+run_tests_verilator.py
+
+# Run specify binary on Verliator core simulation
+./rvb_out/sim-verilator/Vtop_core meminit.bin
+```
+
 ## Generating RISC-V tool-chain
 
 Refer to the following link for instructions on installing the RISC-V software tools:
@@ -36,14 +67,6 @@ Then run after setting the environment variable "RISCV" to your install location
 ./build.sh
 ~~~
 
-## Installing the build environment
-
-RISCVBusiness uses SoCFoundationFlow, built off of the waf build system.  The following repository contains the source for waf:
-
-[SoCFoundationFlow](https://github.com/mattaw/SoCFoundationFlow)
-
-Refer to SoCFoundationFlow for installation instructions.
-
 ## Setup and Run RISCV Business
 
 First, clone the repository