CPU_Project

A SystemVerilog-based verification environment for the ZhenCPU, including FSM, ALU, register, memory testing, waveform analysis, and functional coverage.

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Overview

ZhenCPU is a simplified CPU designed for instruction-level execution and hardware verification learning.
This repository contains:

• RTL source code (SystemVerilog) organized per module
• Self-checking testbenches for each module (ALU, Mem, Mux, Rig, Controller, Counter)
• CPU-level integration testbench
• Waveform analysis using Cadence SimVision
• Functional coverage and simulation support using QuestaSim / ModelSim
• Formal property verification (FPV) for FSM, registers, counters, and ALU
• Instruction program testing environment

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CPU Modules

• ALU – arithmetic & logic operations
• MUX Units – data-path selection
• Register / Rig – accumulator & intermediate registers
• Controller – 8-state Moore FSM for instruction sequencing
• Memory – 8-bit data memory with 5-bit address
• Program Counter – 5-bit counter with enable & reset

All module directories include RTL + testbench + coverage + FPV assertions.

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Verification Features

• ✔ Module-level testbenches (ALU, Mem, Mux, Rig, Control, Counter)
• ✔ CPU integration testing under CPUwave/
• ✔ Directed + randomized stimulus
• ✔ Waveform tracing (VCD/FSDB via SimVision or Questa GUI)
• ✔ Functional coverage using QuestaSim UCDB
• ✔ Simulation logs & automated scripts (runme.sh, runcover.sh, clean.sh)
• ✔ Formal verification (FPV) with bind files

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📁 Project Structure

src/                         # RTL modules + per-module verification environment
  ALU/                       # ALU RTL, ALU testbench, FPV assertions, bind files,
                             # QuestaSim coverage scripts, runme.sh & runcover.sh
  Mem/                       # Memory RTL + memory testbench + FPV + coverage
  Mux/                       # 2-to-1 multiplexer RTL + testbench + coverage
  Rig/                       # 8-bit register RTL + testbench + FPV + coverage
  control/                   # 8-state controller FSM RTL + testbench + FPV + coverage
  count/                     # 5-bit counter / PC RTL + testbench + FPV + coverage
  cpu.sv                     # Top-level CPU module integrating all submodules
  typedefs.sv                # Shared typedefs, enums, opcodes, state definitions

CPUwave/                     # CPU-level waveform simulation environment (Xcelium)
  cpu_tb.sv                  # Full CPU testbench (instruction-level execution)
  runme.sh                   # Launch full CPU simulation + SimVision wave viewer

programs/                    # Instruction program tests + TCL automation scripts
coverage/                    # Consolidated functional coverage reports (UCDB/text)
tb/                          # Additional standalone or experimental testbenches
waves/                       # User-generated waveform screenshots or FSDB exports
.gitignore                   # Files excluded from version control
README.md                    # Project documentation (this file)

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Cadence Xcelium + SimVision (runme.sh)

runme.sh is used for full CPU simulation and waveform debugging using Cadence Xcelium and SimVision.
This script compiles RTL + testbench and opens the waveform viewer.

Typical Flow

./runme.sh      # compile + simulate + open SimVision

Internally, the script performs:

xrun -64bit -access +rwc \
     cpu_tb.sv cpu.sv *.sv \
     -gui

Features

• Fast compile and runtime
• FSDB/SHM waveform viewing through SimVision
• Full SystemVerilog assertion (SVA) support
• Ideal for CPU-level waveform debugging and instruction-level analysis

Output Files

• xrun.log — simulation log
• xcelium.d/ — build directory
• waves.shm/ or .fsdb — waveform database
• simvision_history/ — SimVision GUI state

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QuestaSim Functional Coverage (runcover.sh)

runcover.sh is designed specifically for functional coverage using QuestaSim UCDB.
This script compiles modules, runs the testbench, executes cover.do, and writes coverage reports.

Typical Flow

./runcover.sh    # compile + simulate + generate UCDB coverage

Internally, the script performs:

vlib work
vlog *.sv
vsim -c top_tb -do "do cover.do; run -all; coverage report -output cov.rpt; quit"

Features

• UCDB functional coverage
• FSM, opcode, ALU-path coverage
• Coverage merging and visualization
• Compatible with all per-module testbenches

Output Files

• cov.rpt — text-based coverage report
• work.ucdb — full UCDB coverage database
• transcript — QuestaSim command log

Viewing Coverage in GUI

vsim -viewcov work.ucdb

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JasperGold Formal Verification (run.tcl)

run.tcl is used to run formal verification (FPV) using Cadence JasperGold.
This script clears the environment, analyzes RTL + property files, elaborates the design, and sets clocks/resets.

Example run.tcl Script

# Clear the environment
clear -all

# Analyze design files
analyze -verilog \
    source/design/arbiter.v \
    source/design/port_select.v \
    source/design/bridge.v \
    source/design/egress.v \
    source/design/ingress.v \
    source/design/top.v

# Elaborate design and properties
elaborate -top

# Set up Clocks and Resets
clock clk
reset ~rstN

Running the Script

To execute the Tcl script in JasperGold:

include run.tcl

Launching JasperGold

jg

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